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Intel(R) 82801E Communications I/O Controller Hub (C-ICH)
for Applied Computing
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Product Features
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Supports Intel processors, the 82815E GMCH and the 82810E GMCH 8-Bit Hub Interface -- 266 Mbyte/s maximum throughput Two integrated LAN controllers USB -- Includes one UHCI Host Controller with a total of two ports -- USB 1.1 compliant PCI Bus interface -- Supports PCI Rev 2.2 specification at 33 MHz -- 133 Mbyte/s maximum throughput Low-Pincount (LPC) interface Firmware Hub (FWH) interface -- Supports 8-Mbyte memory size Integrated IDE controller supports Ultra100 DMA, Ultra66 and Ultra33 DMA mode transfers Interrupt Controller -- Two cascaded 82C59 interrupt controllers -- Integrated I/O (x) APIC supporting 24 interrupts -- 15 interrupts supported in 8259 mode
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Two cascaded 8237 DMA controllers Integrated 82C54-compatible timers Real-time clock with 256-byte batterybacked CMOS RAM System Management Bus (SMBus) -- Compatible with most two-wire components that are also I2C compatible -- Slave interface allows external microcontroller to access system resources GPIO -- Exact number varies by configuration. Maximum: 12 inputs, eight outputs, four I/O Integrated 16550 compatible UARTs -- Two UARTs -- Serial Interrupts Supports IRQ1/IRQ12 emulation to avoid external keyboard controller 1.8 V operation with 3.3 V I/O. 5 V tolerance on many buffers, including PCI and IDE Package: 421 BGA
Notice: This document contains information on products in the sampling and initial production phases of development. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.
Order Number: 273598-003 January 2002
Information in this document is provided in connection with Intel(R) products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel(R) 82801E Communications I/O Controller Hub may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) Intel Corporation, 2002 AlertVIEW, i960, AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, Commerce Cart, CT Connect, CT Media, Dialogic, DM3, EtherExpress, ETOX, FlashFile, GatherRound, i386, i486, iCat, iCOMP, Insight960, InstantIP, Intel, Intel logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel ChatPad, Intel Create&Share, Intel Dot.Station, Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel NetBurst, Intel NetStructure, Intel Play, Intel Play logo, Intel Pocket Concert, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel TeamStation, Intel WebOutfitter, Intel Xeon, Intel XScale, Itanium, JobAnalyst, LANDesk, LanRover, MCS, MMX, MMX logo, NetPort, NetportExpress, Optimizer logo, OverDrive, Paragon, PC Dads, PC Parents, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, ProShare, RemoteExpress, Screamline, Shiva, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside, The Journey Inside, This Way In, TokenExpress, Trillium, Vivonic, and VTune are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others.
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Contents
Contents
1.0 Introduction....................................................................................................................................7 1.1 1.2 2.0 Overview ............................................................................................................................... 9 About this Document .......................................................................................................... 10
Package Information ................................................................................................................... 11 2.1 2.2 Ball Location ....................................................................................................................... 11 Mechanical Specifications .................................................................................................. 23
3.0
Signal Descriptions ..................................................................................................................... 25 3.1 3.2 Alphabetical Signal Reference............................................................................................25 Signals Grouped By Type ................................................................................................... 36 3.2.1 Hub Interface to Host Controller ............................................................................ 36 3.2.2 Link to LAN Connect .............................................................................................. 36 3.2.3 EEPROM Interface ................................................................................................ 36 3.2.4 Firmware Hub Interface ......................................................................................... 37 3.2.5 PCI Interface .......................................................................................................... 37 3.2.6 IDE Interface .......................................................................................................... 40 3.2.7 LPC Interface ......................................................................................................... 41 3.2.8 Interrupt Interface .................................................................................................. 41 3.2.9 USB Interface ........................................................................................................42 3.2.10 Power Signals ........................................................................................................42 3.2.11 Processor Interface................................................................................................ 43 3.2.12 SMBus Interface .................................................................................................... 44 3.2.13 System Management Interface ..............................................................................44 3.2.14 Real Time Clock Interface .....................................................................................44 3.2.15 Other Clocks .......................................................................................................... 45 3.2.16 Universal Asynchronous Receive and Transmit (UART 0,1) .................................45 3.2.17 SIU LPC Interface .................................................................................................. 46 3.2.18 Miscellaneous Signals ........................................................................................... 47 3.2.19 General Purpose I/O .............................................................................................. 47 3.2.20 Power and Ground.................................................................................................48 Pin Straps ...........................................................................................................................49 3.3.1 Functional Straps ................................................................................................... 49 3.3.2 Test Signals ........................................................................................................... 49 3.3.2.1 Test Mode Selection ..............................................................................49 3.3.2.2 Test Straps............................................................................................. 50 3.3.3 External RTC Circuitry ........................................................................................... 50 3.3.4 V5REF/Vcc3_3 Sequencing Requirements ...........................................................51 Power Planes and Pin States ............................................................................................. 51 3.4.1 Power Planes......................................................................................................... 51 3.4.2 Integrated Pull-Ups and Pull-Downs ...................................................................... 52 3.4.3 IDE Integrated Series Termination Resistors......................................................... 52 3.4.4 Output and I/O Signals Planes and States ............................................................ 53 3.4.5 Power Planes for Input Signals..............................................................................55
3.3
3.4
4.0
Electrical Characteristics............................................................................................................ 57 4.1 Absolute Maximum Ratings ................................................................................................ 57
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Contents
4.2 4.3 4.4 4.5 5.0
Functional Operating Range............................................................................................... 57 DC Characteristics.............................................................................................................. 58 AC Characteristics .............................................................................................................. 62 Timing Diagrams................................................................................................................. 70
Testability..................................................................................................................................... 77 5.1 5.2 5.3 Test Mode Description........................................................................................................ 77 Tri-state Mode..................................................................................................................... 78 XOR Chain Mode................................................................................................................ 78 5.3.1 XOR Chain Testability Algorithm Example ............................................................ 84 5.3.1.1 Test Pattern Consideration for XOR Chain 4......................................... 84
Figures
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 System Configuration ................................................................................................................... 7 Intel(R) 82801E C-ICH Simplified Block Diagram ........................................................................... 8 Ball Diagram (Top View)............................................................................................................. 11 Intel(R) 82801E C-ICH Package (Top View) ................................................................................. 23 Intel(R) 82801E C-ICH Package (Side View) ................................................................................ 24 Intel(R) 82801E C-ICH Package (Bottom View)............................................................................ 24 Required External RTC Circuit ................................................................................................... 50 Example V5REF Sequencing Circuit .......................................................................................... 51 Clock Timing ............................................................................................................................... 70 Valid Delay From Rising Clock Edge.......................................................................................... 70 Setup And Hold Times................................................................................................................ 71 Float Delay ................................................................................................................................. 71 Pulse Width ................................................................................................................................ 71 Output Enable Delay .................................................................................................................. 71 IDE PIO Mode ............................................................................................................................ 72 IDE Multiword DMA .................................................................................................................... 72 Ultra ATA Mode (Drive Initiating a Burst Read) .......................................................................... 73 Ultra ATA Mode (Sustained Burst) ............................................................................................. 73 Ultra ATA Mode (Pausing a DMA Burst) .................................................................................... 74 Ultra ATA Mode (Terminating a DMA Burst) .............................................................................. 74 USB Rise and Fall Times ........................................................................................................... 74 USB Jitter ................................................................................................................................... 75 USB EOP Width ......................................................................................................................... 75 SMBus Transaction .................................................................................................................... 75 SMBus Time-out ......................................................................................................................... 75 Power Sequencing and Reset Signal Timings ........................................................................... 76 1.8 V/3.3 V Power Sequencing................................................................................................... 76 C0 to C2 to C0 Timings .............................................................................................................. 76 Test Mode Entry (XOR Chain Example)..................................................................................... 77 Example XOR Chain Circuitry .................................................................................................... 78
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Contents
Tables
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 PCI Devices and Functions ..........................................................................................................9 Related Documents ....................................................................................................................10 Industry Specifications................................................................................................................ 10 Ball List By Number ....................................................................................................................12 Ball List By Signal Name ............................................................................................................ 17 82801E C-ICH Signal Description .............................................................................................. 25 Hub Interface Signals ................................................................................................................. 36 LAN Interface.............................................................................................................................. 36 EEPROM Interface ..................................................................................................................... 36 Firmware Hub Interface Signals .................................................................................................37 PCI Interface Signals .................................................................................................................. 37 IDE Interface Signals .................................................................................................................. 40 LPC Interface Signals ................................................................................................................. 41 Interrupt Signals.......................................................................................................................... 41 USB Interface Signals................................................................................................................. 42 Power Signals............................................................................................................................. 42 Processor Interface Signals ........................................................................................................43 SMBus Interface Signals ............................................................................................................ 44 System Management Interface Signals ...................................................................................... 44 Real Time Clock Interface .......................................................................................................... 44 Other Clocks ............................................................................................................................... 45 Universal Asynchronous Receive And Transmit (UART 0, 1) ....................................................45 SIU Interface............................................................................................................................... 46 Miscellaneous Signals ................................................................................................................ 47 General Purpose I/O Signals ...................................................................................................... 47 Power and Ground Signals......................................................................................................... 48 Functional Strap Definitions ........................................................................................................49 Test Mode Selection ................................................................................................................... 49 82801E C-ICH Power Planes ..................................................................................................... 51 Integrated Pull-Up and Pull-Down Resistors ..............................................................................52 IDE Series Termination Resistors............................................................................................... 52 Power Plane and States for Output and I/O Signals................................................................... 53 Power Plane for Input Signals ................................................................................................ .... 56 Absolute Maximum Ratings ........................................................................................................57 Functional Operating Range....................................................................................................... 57 82801E C-ICH Power Consumption Measurements ..................................................................58 DC Characteristic Input Signal Association ................................................................................ 58 DC Input Characteristics............................................................................................................. 59 DC Characteristic Output Signal Association ............................................................................. 59 DC Output Characteristics .......................................................................................................... 60 Other DC Characteristics............................................................................................................ 61 Clock Timings ............................................................................................................................. 62 Clock Timings - UART_CLK ....................................................................................................... 63 PCI Interface Timing ................................................................................................................... 63 IDE PIO & Multiword DMA Mode Timing .................................................................................... 64 Ultra ATA Timing (Mode 0, Mode 1, Mode 2) ............................................................................. 65 Ultra ATA Timing (Mode 3, Mode 4, Mode 5) ............................................................................. 66 Universal Serial Bus Timing........................................................................................................67 IOAPIC Bus Timing..................................................................................................................... 68
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Contents
50 51 52 53 54 55 56 57 58 59 60 61 62
SMBus Timing ............................................................................................................................ 68 SIU LPC and Serial IRQ Timings ............................................................................................... 68 UART Timings ............................................................................................................................ 69 LPC Timing ................................................................................................................................. 69 Miscellaneous Timings ............................................................................................................... 69 Power Sequencing and Reset Signal Timings ........................................................................... 70 Test Mode Selection ................................................................................................................... 77 XOR Chain #1 ............................................................................................................................ 79 XOR Chain #2; Chain 2-1 and Chain 2-2 ................................................................................... 80 XOR Chain #3; Chain 3-1 and Chain 3-2 ................................................................................... 81 XOR Chain #4; Chain 4-1 and Chain 4-2 ................................................................................... 82 Signals Not in XOR Chain .......................................................................................................... 83 XOR Test Pattern Example ........................................................................................................ 84
Revision History
Date January 2001 December 2001 December 2001 Revision 003 002 001 Description Corrected XOR Chain 2. Added note to CPUSLP# signal description. Corrected pinouts and pin list. First release of this datasheet.
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Intel(R) 82801E C-ICH
1.0
Introduction
The Intel(R) 82801E Communications I/O Controller Hub (82801E C-ICH) is a highly integrated multifunctional communications I/O controller hub that provides the interface to the PCI bus and integrates many of the functions needed in today's communications applications. This document provides a detailed description of the 82801E C-ICH thermal, electrical and mechanical specifications, including signals, pinout, packaging, electrical characteristics, and testability. Figure 1 illustrates the typical system configuration using the 82801E C-ICH. Figure 2 is a simplified block diagram of the functional units of the 82801E C-ICH.
Figure 1. System Configuration
Processor
Graphics Controller
Host Controller
Main Memory
Hub Interface SMBus Device(s) ATA/100/66/33 4 IDE Drives Two USB Ports GPIO Two LAN Controllers Two UARTs Communications I/O Controller Hub (C-ICH) LPC I/F SMBus
Up to Four PCI Slots PCI Bus
FWH
sys_blk_CICH.vsd
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7
Intel(R) 82801E C-ICH
Figure 2. Intel(R) 82801E C-ICH Simplified Block Diagram
SPKR RTCRST# TP[3:0] PDCS1# SDCS1# PDCS3# SDCS3# PDA[2:0] SDA[2:0] PDD[15:0] SDD[15:0] PDDREQ SDDREQ PDDACK# SDDACK# PDIOR# SDIOR# PDIOW# SDIOW# PIORDY SIORDY A20M# CPUSLP# FERR# IGNNE# INIT# INTR NMI SMI# STPCLK# RCIN# A20GATE CPUPWRGD SERIRQ PIRQ[A:F]# PIRQ[G:H]/GPIO[5:4] IRQ[15:14] APICCLK APICD[1:0] USBP1P USBP1N USBP0P USBP0N OC[1:0]# RTCX1 RTCX2 CLK14 CLK48 CLK66 GPIO[13:11,8:4,1:0] GPIO[23:16] GPIO[28:27,25:24] EE0_SHCLK EE0_DIN EE0_DOUT EE0_CS SIU_LCLK SIU0_RXD SIU0_TXD SIU0_CTS# SIU0_DSR# SIU0_DCD# SIU0_RI# SIU0_DTR# SIU0_RTS# SIU_RESET# SIU_LAD[3:0] THRM# RI# SUSCLK AD[31:0] C/BE[3:0]# DEVSEL# FRAME# IRDY# TRDY# STOP# PAR PERR# REQ[3:0]# REQ[5]#/REQ[B]#/GPIO[1] REQ[A]#/GPIO[0] GNT[3:0]# GNT[5]#/GNT[B]#/GPIO[17] GNT[A]#/GPIO[16] PCICLK PCIRST# PLOCK# SERR# PWROK RSMRST# RSM_PWROK VRMPWRGD HL[11:0] HL_STB HL_STB# HLCOMP FWH[3:0]/LAD[3:0] FWH[4]/LFRAME# LAD[3:0]/FWH[3:0] LFRAME#/FWH[4] LDRQ[1:0]# SMBDATA SMBCLK SMBALERT#/GPIO[11] INTRUDER# SMLINK[1:0] LAN0_CLK LAN0_RXD[2:0] LAN0_TXD[2:0] LAN0_RSTSYNC LAN1_CLK LAN1_RXD[2:0] LAN1_TXD[2:0] LAN1_RSTSYNC EE1_SHCLK EE1_DIN EE1_DOUT EE1_CS UART_CLK SIU1_RXD SIU1_TXD SIU1_CTS# SIU1_DSR# SIU1_DCD# SIU1_RI# SIU1_DTR# SIU1_RTS# SIU_LFRAME# SIU_LDRQ# SIU_SERIRQ
Blk_CICH.vsd
Miscellaneous Signals
IDE Interface PCI Interface
Processor Interface
Power Signals
Hub Interface
Firmware Hub Interrupt LPC Interface SMBus Interface System Management
USB
RTC
Clocks
LAN0
General Purpose I/O
LAN1
EEPROM0
EEPROM1
Serial I/O Unit
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Advance Information Datasheet
Intel(R) 82801E C-ICH
1.1
Overview
The 82801E C-ICH provides extensive I/O support. Functions and capabilities include:
* * * * * * * * * *
PCI Rev 2.2 compliant with support for 33 MHz PCI operations PCI slots support up to four Req/Gnt pairs Enhanced DMA Controller, Interrupt Controller, and Timer Functions Integrated IDE controller supports Ultra ATA100/66/33 USB host interface with support for two USB ports; one host controller Two integrated LAN controllers System Management Bus (SMBus) with additional support for I2C devices Low Pin Count (LPC) interface Firmware Hub (FWH) interface support Serial I/O unit containing two UARTs
The 82801E C-ICH incorporates a variety of PCI functions that are divided into two logical devices (30 and 31) on PCI Bus 0 and one device on Bus 1. Device 30 is the Hub Interface-to-PCI bridge. Device 31 contains all the other PCI functions, except the LAN controller as shown in Table 1. The LAN controllers are located on Bus 1. Table 1. PCI Devices and Functions
Bus:Device:Function Bus 0:Device 30:Function 0 Function Description Hub Interface to PCI Bridge PCI to LPC Bridge (includes: DMA, Timers, compatible interrupt controller, APIC, RTC, SIU, processor interface control, power management control, system management control, and GPIO control) IDE Controller USB Controller SMBus Controller LAN0 Controller LAN1 Controller
Bus 0:Device 31:Function 0
Bus 0:Device 31:Function 1 Bus 0:Device 31:Function 2 Bus 0:Device 31:Function 3 Bus 1:Device 8:Function 0 Bus 1:Device 9:Function 0
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Intel(R) 82801E C-ICH
1.2
About this Document
This document is intended for original equipment manufacturers (OEMs) and BIOS vendors creating 82801E C-ICH-based products. This document contains electrical thermal and mechanical specifications for the 82801E C-ICH, including complete signal descriptions, pin maps, and testability information. For additional information, refer to the documents listed in Table 2.
Table 2.
Related Documents
Document Order Number 273599 273645 273671 290676 290658
Intel(R) 82801E Communications I/O Controller Hub (C-ICH) Developer's Manual Intel(R) 82801E Communications I/O Controller Hub (C-ICH) Specification Update Intel 82801E Communications I/O Controller Hub (C-ICH) Platform Design Guide Intel 810E Chipset: 82810E Graphics and Memory Controller Hub (GMCH) Datasheet 82802AB/82802AC Firmware Hub (FWH) Datasheet
(R) (R)
This document assumes a working knowledge of the vocabulary and principles of USB, IDE, SMBus, PCI, LAN, LPC, and serial I/O. Details of these features are described in the Intel(R) 82801E Communications I/O Controller Hub (C-ICH) Developer's Manual (order number 273599) and in the industry specifications listed in Table 3. Table 3. Industry Specifications
Specification LPC WfM SMBus PCI USB Location http://developer.intel.com/design/chipsets/industry/lpc.htm http://developer.intel.com/ial/WfM/usesite.htm http://www.sbs-forum.org/specs/ http://pcisig.com/ http://www.usb.org
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Intel(R) 82801E C-ICH
2.0
2.1
Package Information
Ball Location
This section describes the 82801E C-ICH ball assignment. Figure 3 provides a 421-ball location diagram. The diagram also indicates general signal groupings. Table 4 lists the 82801E C-ICH signal assignments by ball number. Table 5 lists the assignments alphabetically by signal name.
Figure 3. Ball Diagram (Top View)
PCI
1 A
VSS AD[28] GNT[3]# NC[4] PIRQ[A]# VSS PIRQ[H]#/ GNT[0]# GPIO[5] VSS GPIO[21] THRM# TP[0] VSS SIU_ SIU_ SIU1_ SERIRQ LAD[1] RTS# VSS SIU1_ UART_ DSR# CLK SIU1_ RXD SIU0_ DTR# VSS VSS SIU0_ RI# LAN1_ CLK LAN1_ TXD[1] Vcc1_8 VSS
LPC
7 8 9 10 11 12 13 14 15
SIU
16 17 18 19 20 21 22 23 A
2
3
4
5
6
B C
FRAME# AD[16] AD[22]
SIU1_ VCC3_3 AD[26] REQ[0]# NC[5] PIRQ[D]# VCC1_8 GNT[B]#/ GNT[A]#/LDRQ[0]# LAD[0]/ LAD[3]/ Vcc1_8 SIU_ GNT[5]#/ GPIO[16] FWH[0] FWH[3] LFRAME# DTR#
GPIO[17]
SIU0_ DCD#
LAN1_ RXD[2]
B C
AD[13]
AD[20]
PAR
VSS
AD[30]
VSS
PIRQ[C]# PIRQ[E]#REQ[A]#/REQ[B]#/ LDRQ[1]# VSS LFRAME#/ SIU_ FWH[4] LAD[2] GPIO[0] REQ[5]#/
GPIO[1]
SIU_ LDRQ#
SIU1_ DCD#
SIU1_ Vcc3_3 TXD
LAN1_ LAN1_ LAN1_ EE0_ TXD[0] RXD[0] RSTSYNC SHCLK
D
VSS AD[4] AD[15] STOP# AD[18] AD[24] REQ[1]# PIRQ[B]# VSS
D E F
Vcc1_8 EE0_CS Vcc1_8 LAN0_CLK
E F G
AD[0]
Vcc1_8 AD[9]
TRDY#
VSS
Vcc3_3
VSS
PIRQ[G]#/ LAD[2]/ GNT[2]# REQ[2]# PIRQ[F]# GPIO[4] FWH[2]
SIU_ LCLK
SIU_ LAD[3]
VSS
SIU0_ RTS#
SIU0_ RXD
VSS Vcc3_3
EE1_ SHCLK
EE0_ DIN
LAN0_ RXD[2]
LAN0_ TXD[2]
AD[7]
AD[10]
AD[6] C/BE[0]# AD[11] Vcc3_3 Vcc3_3 Vcc1_8
Vcc1_8 Vcc1_8
Vcc1_8 Vcc3_3
Vcc3_3 Vcc3_3 Vcc3_3 EE1_CS
G
SERR# AD[12] VSS AD[3] AD[2] Vcc3_3 Vcc3_3 EE1_ DIN EE0_ DOUT LAN0_ TXD[1] VSS LAN0_ RXD[1]
PCI
H
C/BE[1]# AD[14] AD[8] AD[1] AD[5] Vcc3_3 Vcc3_3 LAN1_ LAN0_ RXD[1] RXD[0] LAN0_ Vcc1_8 TXD[0] VSS
H J
VSS PERR# C/BE[2]# DEVSEL# VSS Vcc3_3 Vcc1_8 VSS VSS VSS VSS CLK66 (HLCLK) Vcc1_8 VSS Vcc1_8 VSS Vcc1_8
J K
AD[23] AD[19] AD[17] IRDY# PLOCK# Vcc3_3
Vcc1_8
HLCOMP
HUBREF
VSS
HL[11]
VSS
L
AD[27] AD[25] VSS C/BE[3]# AD[21]
VSS
VSS
VSS
VSS
Vcc1_8
HL[0]
VSS
HL[1]
VSS
HL[2]
L M
M
AD[29] AD[31] GPIO[6] REQ[3]# PCICLK Vcc1_8 VSS VSS VSS Vcc1_8 HL[9] HL[3] VSS HL_STB VSS
N P R
VSS GPIO[7]
GPIO[27] GPIO[28]
Vcc1_8
N
VSS VSS VSS VSS VSS HL[4] VSS HL[10] VSS HL_STB# Vcc3_3
GPIO[8] GPIO[12]
VSS GPIO[13] RESERVED1
Vcc1_8
VSS
Vcc1_8
VSS
Vcc1_8
Vcc1_8
HL[7]
HL[5]
VSS
HL[8]
VSS
P R
PCIRST# RI# Vcc3_3 GPIO[25] SMBDATA
Vcc3_3
CPUSLP# Vcc1_8
VSS
VSS
VSS
HL[6]
SMBUS
T
VSS USBP0N RSM_PWROK Vcc3_3 NC[12] SMBCLK GPIO[20] Vcc1_8 GPIO[23] SMI# STPCLK# A20M#
T U
SMBALERT#/ NC[11] SUSCLK USBP0P GPIO[11]
U
VSS Vcc3_3 Vcc3_3 SDCS1# GPIO[22] INIT# NMI INTR
V
NC[10] USBP1N Vcc3_3 NC[6] V5REF Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3
V
SDDACK# V_CPU_IO IGNNE# Vcc3_3 SIORDY CPUPWRGD
USB
W
USBP1P NC[9] NC[7] OC[1]# VSS VSS NC[1] VccRTC PWROK Vcc3_3 CLK14 PDD[5] PDD[1] PDCS1# PDA[1] SDD[5] SDD[14] SDIOW# VRMPWRGD RCIN# SDIOR# SDA[2] V_CPU_IO SDD[0] SDCS3# A20GATE GPIO[18]
W
VSS NC[8] SMLINK[0] VSS V5REF RESERVED2 RTCX1 RSMRST# NC[2] APICD[1] PDD[6] PDD[10] PDD[12] SDD[6] PDIOW# PDA[0] SDD[10]
Y AA
Y AA
SDD[12]
SDD[15]
OC0#
VSS
VSS SMLINK[1]
TP[1] RTCRST#
RTCX2 VccRTC FERR# SERIRQ PDD[7]
VSS
PDD[3] PDD[0] PDDACK# VSS
SDD[8]
SDD[4] SDD[3]
VSS
SDA[1]
VSS
GPIO[19]
AB AC
V5REF
TP[3]
Vcc3_3
INTRUDER# GPIO[24] VBIAS
VSS
CLK48 APICD[0] SPKR
PDD[8] PDD[4] PDD[13] PDD[14]
PDD[15] IRQ[14] PDIOR# SDD[9] SDD[11] SDD[13] Vcc3_3 IRQ[15] SDA[0]
AB AC
VSS
TP[2]
VSS
VSS
VSS
VSS
NC[3]
VSS APICCLK
V5REF
PDD[9]
PDD[11]
VSS
PDD[2]
PDDREQ
PDA[2]
PIORDY
SDD[7]
PDCS3#
SDD[2]
SDD[1]
SDDREQ
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16 17
18
19
20 21
22
23
A8684-02
POWER MANAGEMENT
SMLINK
IDE
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IDE
PROCESSOR
HUB INTERFACE
K
LAN
SIU_ GNT[1]# V5REF LAD[1]/ SIU_ FWH[1] RESET# LAD[0]
SIU1_ RI#
SIU1_ CTS#
SIU0_ CTS#
SIU0_ DSR#
SIU0_ TXD
LAN1_ TXD[2]
EE1_ DOUT
VSS
LAN0_ RSTSYNC
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Intel(R) 82801E C-ICH
Table 4.
Ball Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20
Ball List By Number
Signal Name VSS AD[28] GNT[3]# NC[4] PIRQ[A]# VSS PIRQ[H]#/GPIO[5] GNT[0]# VSS GPIO[21] THRM# TP[0] VSS SIU_SERIRQ SIU_LAD[1] SIU1_RTS# VSS SIU1_DSR# UART_CLK VSS SIU0_RI# LAN1_TXD[1] VSS FRAME# AD[16] AD[22] AD[26] REQ[0]# NC[5] PIRQ[D]# Vcc1_8 GNT[B]#/GNT[5]#/GPIO[17] GNT[A]#/GPIO[16] LDRQ[0]# LAD[0]/FWH[0] LAD[3]/FWH[3] Vcc1_8 SIU_LFRAME# SIU1_DTR# Vcc3_3 SIU1_RXD SIU0_DTR# SIU0_DCD#
Table 4.
Ball Number B21 B22 B23 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18
Ball List By Number
Signal Name LAN1_CLK Vcc1_8 LAN1_RXD[2] AD[13] AD[20] PAR VSS AD[30] VSS PIRQ[C]# PIRQ[E]# REQ[A]#/GPIO[0] REQ[B]#/REQ[5]#/GPIO[1] LDRQ[1]# VSS LFRAME#/FWH[4] SIU_LAD[2] SIU_LDRQ# SIU1_DCD# SIU1_TXD Vcc3_3 VSS LAN1_TXD[0] LAN1_RXD[0] LAN1_RSTSYNC EE0_SHCLK VSS AD[4] AD[15] STOP# AD[18] AD[24] REQ[1]# PIRQ[B]# VSS GNT[1]# V5REF LAD[1]/FWH[1] SIU_RESET# SIU_LAD[0] SIU1_RI# SIU1_CTS# SIU0_CTS# SIU0_DSR#
12
Advance Information Datasheet
Intel(R) 82801E C-ICH
Table 4.
Ball Number D19 D20 D21 D22 D23 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F14 F15 F16 F17 F18 F19
Ball List By Number
Signal Name SIU0_TXD LAN1_TXD[2] EE1_DOUT VSS LAN0_RSTSYNC AD[0] Vcc1_8 AD[9] TRDY# VSS Vcc3_3 VSS GNT[2]# REQ[2]# PIRQ[F]# PIRQ[G]#/GPIO[4] LAD[2]/FWH[2] SIU_LCLK SIU_LAD[3] VSS SIU0_RTS# SIU0_RXD Vcc3_3 VSS EE1_SHCLK EE0_DIN LAN0_RXD[2] LAN0_TXD[2] AD[7] AD[10] AD[6] C/BE[0]# AD[11] Vcc3_3 Vcc3_3 Vcc1_8 Vcc1_8 Vcc1_8 Vcc1_8 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 EE1_CS
Table 4.
Ball Number F20 F21 F22 F23 G1 G2 G3 G4 G5 G6 G18 G19 G20 G21 G22 G23 H1 H2 H3 H4 H5 H6 H18 H19 H20 H21 H22 H23 J1 J2 J3 J4 J5 J6 J18 J19 J20 J21 J22 J23 K1 K2 K3 K4
Ball List By Number
Signal Name EE0_CS Vcc1_8 LAN0_CLK Vcc1_8 SERR# AD[12] VSS AD[3] AD[2] Vcc3_3 Vcc3_3 EE1_DIN EE0_DOUT LAN0_TXD[1] VSS LAN0_RXD[1] C/BE[1]# AD[14] AD[8] AD[1] AD[5] Vcc3_3 Vcc3_3 LAN1_RXD[1] LAN0_RXD[0] LAN0_TXD[0] Vcc1_8 VSS VSS C/BE[2]# DEVSEL# PERR# VSS Vcc3_3 Vcc1_8 VSS VSS VSS VSS CLK66 (HLCLK) AD[23] AD[19] AD[17] IRDY#
Advance Information Datasheet
13
Intel(R) 82801E C-ICH
Table 4.
Ball Number K5 K6 K10 K11 K12 K13 K14 K18 K19 K20 K21 K22 K23 L1 L2 L3 L4 L5 L10 L11 L12 L13 L14 L19 L20 L21 L22 L23 M1 M2 M3 M4 M5 M10 M11 M12 M13 M14 M19 M20 M21 M22 M23 N1
Ball List By Number
Signal Name PLOCK# Vcc3_3 Vcc1_8 VSS Vcc1_8 VSS Vcc1_8 Vcc1_8 HLCOMP HUBREF VSS HL[11] VSS AD[27] AD[25] VSS C/BE[3]# AD[21] VSS VSS VSS VSS Vcc1_8 HL[0] VSS HL[1] VSS HL[2] AD[29] AD[31] GPIO[6] REQ[3]# PCICLK Vcc1_8 VSS VSS VSS Vcc1_8 HL[9] HL[3] VSS HL_STB VSS VSS
Table 4.
Ball Number N2 N3 N4 N5 N10 N11 N12 N13 N14 N19 N20 N21 N22 N23 P1 P2 P3 P4 P5 P6 P10 P11 P12 P13 P14 P18 P19 P20 P21 P22 P23 R1 R2 R3 R4 R5 R6 R18 R19 R20 R21 R22 R23 T1
Ball List By Number
Signal Name GPIO[7] GPIO[27] GPIO[28] Vcc1_8 VSS VSS VSS VSS VSS HL[4] VSS HL[10] VSS HL_STB# GPIO[8] GPIO[12] GPIO[13] RESERVED1 VSS Vcc3_3 Vcc1_8 VSS Vcc1_8 VSS Vcc1_8 Vcc1_8 HL[7] HL[5] VSS HL[8] VSS PCIRST# GPIO[25] Vcc3_3 SMBDATA RI# Vcc3_3 Vcc1_8 CPUSLP# VSS VSS VSS HL[6] VSS
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Intel(R) 82801E C-ICH
Table 4.
Ball Number T2 T3 T4 T5 T6 T18 T19 T20 T21 T22 T23 U1 U2 U3 U4 U5 U6 U18 U19 U20 U21 U22 U23 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23
Ball List By Number
Signal Name SMBCLK RSM_PWROK NC[12] USBP0N Vcc3_3 Vcc1_8 GPIO[20] GPIO[23] SMI# STPCLK# A20M# SMBALERT#/GPIO[11] NC[11] SUSCLK USBP0P VSS Vcc3_3 Vcc3_3 SDCS1# GPIO[22] INIT# NMI INTR NC[10] USBP1N Vcc3_3 NC[6] V5REF Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 SDDACK# SIORDY (/SDRSTB/ SWDMARDY#) V_CPU_IO CPUPWRGD IGNNE#
Table 4.
Ball Number W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20
Ball List By Number
Signal Name USBP1P NC[9] NC[7] OC[1]# VSS VSS NC[1] VccRTC PWROK Vcc3_3 CLK14 PDD[5] PDD[1] PDCS1# PDA[1] SDD[5] SDD[14] SDIOR# (/SDWSTB/ SRDMARDY#) SDIOW# (/SDSTOP) SDA[2] VRMPWRGD V_CPU_IO RCIN# VSS NC[8] V5REF RESERVED2 SMLINK[0] VSS RTCX1 RSMRST# NC[2] APICD[1] PDD[6] PDD[10] PDD[12] PDIOW# (/PDSTOP) SDD[6] PDA[0] SDD[10] SDD[12] SDD[0] SDD[15]
Advance Information Datasheet
15
Intel(R) 82801E C-ICH
Table 4.
Ball Number Y21 Y22 Y23 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11
Ball List By Number
Signal Name SDCS3# GPIO[18] A20GATE OC[0]# VSS VSS SMLINK[1] TP[1] RTCRST# RTCX2 VccRTC FERR# SERIRQ PDD[7] VSS PDD[3] PDD[0] PDDACK# VSS SDD[8] SDD[4] SDD[3] VSS SDA[1] VSS GPIO[19] V5REF TP[3] Vcc3_3 GPIO[24] INTRUDER# VBIAS VSS CLK48 APICD[0] SPKR PDD[8]
Table 4.
Ball Number AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23
Ball List By Number
Signal Name PDD[4] PDD[13] PDD[14] PDD[15] IRQ[14] PDIOR# (/PDWSTB/ PRDMARDY#) SDD[9] SDD[11] SDD[13] Vcc3_3 IRQ[15] SDA[0] VSS TP[2] VSS VSS VSS VSS NC[3] VSS APICCLK V5REF PDD[9] PDD[11] VSS PDD[2] PDDREQ PDA[2] PIORDY (/PDRSTB/ PWDMARDY#) SDD[7] PDCS3# SDD[2] SDD[1] SDDREQ VSS
16
Advance Information Datasheet
Intel(R) 82801E C-ICH
Table 5.
Ball List By Signal Name
Ball Number Y23 T23 E1 H4 G5 G4 D2 H5 F3 F1 H3 E3 F2 F5 G2 C1 H2 D3 B2 K3 D5 K2 C2 L5 B3 K1 D6 L2 B4 L1 A2 M1 C5 M2 AC9 AB9 Y10
Table 5.
Ball List By Signal Name
Ball Number F4 H1 J2 L4 W11 AB8 J23 V22 R19 J3 F20 E21 G20 C23 F19 G19 D21 E20 AA9 B1 A8 D10 E8 A3 B10 B9 M3 N2 P1 P2 P3 Y22 AA23 T19 A10 U20 T20 AB4
Signal Name A20GATE A20M# AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6] AD[7] AD[8] AD[9] AD[10] AD[11] AD[12] AD[13] AD[14] AD[15] AD[16] AD[17] AD[18] AD[19] AD[20] AD[21] AD[22] AD[23] AD[24] AD[25] AD[26] AD[27] AD[28] AD[29] AD[30] AD[31] APICCLK APICD[0] APICD[1]
Signal Name C/BE[0]# C/BE[1]# C/BE[2]# C/BE[3]# CLK14 CLK48 CLK66 (HLCLK) CPUPWRGD CPUSLP# DEVSEL# EE0_CS EE0_DIN EE0_DOUT EE0_SHCLK EE1_CS EE1_DIN EE1_DOUT EE1_SHCLK FERR# FRAME# GNT[0]# GNT[1]# GNT[2]# GNT[3]# GNT[A]#/GPIO[16] GNT[B]#/GNT[5]#/GPIO[17] GPIO[6] GPIO[7] GPIO[8] GPIO[12] GPIO[13] GPIO[18] GPIO[19] GPIO[20] GPIO[21] GPIO[22] GPIO[23] GPIO[24]
Advance Information Datasheet
17
Intel(R) 82801E C-ICH
Table 5.
Ball List By Signal Name
Ball Number R2 N3 N4 L19 L21 L23 M20 N19 P20 R23 P19 P22 M19 N21 K22 M22 N23 K19 K20 V23 U21 U23 AB5 K4 AB16 AB22 B12 D12 E12 B13 F22 D23 H20 G23 E22 H21 G21 E23
Table 5.
Ball List By Signal Name
Ball Number B21 C22 C21 H19 B23 C20 A22 D20 B11 C11 C13 W7 Y9 AC7 A4 B6 V4 W3 Y2 W2 V1 U2 T4 U22 AA1 W4 C3 M5 R1 Y16 W15 AC16 W14 AC19 AA14 W13 AC14 AA13
Signal Name GPIO[25] GPIO[27] GPIO[28] HL[0] HL[1] HL[2] HL[3] HL[4] HL[5] HL[6] HL[7] HL[8] HL[9] HL[10] HL[11] HL_STB HL_STB# HLCOMP HUBREF IGNNE# INIT# INTR INTRUDER# IRDY# IRQ[14] IRQ[15] LAD[0]/FWH[0] LAD[1]/FWH[1] LAD[2]/FWH[2] LAD[3]/FWH[3] LAN0_CLK LAN0_RSTSYNC LAN0_RXD[0] LAN0_RXD[1] LAN0_RXD[2] LAN0_TXD[0] LAN0_TXD[1] LAN0_TXD[2]
Signal Name LAN1_CLK LAN1_RSTSYNC LAN1_RXD[0] LAN1_RXD[1] LAN1_RXD[2] LAN1_TXD[0] LAN1_TXD[1] LAN1_TXD[2] LDRQ[0]# LDRQ[1]# LFRAME#/FWH[4] NC[1] NC[2] NC[3] NC[4] NC[5] NC[6] NC[7] NC[8] NC[9] NC[10] NC[11] NC[12] NMI OC[0]# OC[1]# PAR PCICLK PCIRST# PDA[0] PDA[1] PDA[2] PDCS1# PDCS3# PDD[0] PDD[1] PDD[2] PDD[3]
18
Advance Information Datasheet
Intel(R) 82801E C-ICH
Table 5.
Ball List By Signal Name
Ball Number AB12 W12 Y11 AA11 AB11 AC11 Y12 AC12 Y13 AB13 AB14 AB15 AA15 AC15 AB17 Y14 J4 AC17 A5 D8 C7 B7 C8 E10 E11 A7 K5 W9 W23 B5 D7 E9 M4 C9 C10 P4
Table 5.
Ball List By Signal Name
Ball Number Y4 R5 T3 Y8 AA6 Y7 AA7 AB23 AA21 W20 U19 Y21 Y19 AC21 AC20 AA19 AA18 W16 Y15 AC18 AA17 AB18 Y17 AB19 Y18 AB20 W17 Y20 V19 AC22 W18 W19 AA10 G1 V20 D14
Signal Name PDD[4] PDD[5] PDD[6] PDD[7] PDD[8] PDD[9] PDD[10] PDD[11] PDD[12] PDD[13] PDD[14] PDD[15] PDDACK# PDDREQ PDIOR# (/PDWSTB/ PRDMARDY#) PDIOW# (/PDSTOP) PERR# PIORDY (/PDRSTB/ PWDMARDY#) PIRQ[A]# PIRQ[B]# PIRQ[C]# PIRQ[D]# PIRQ[E]# PIRQ[F]# PIRQ[G]#/GPIO[4] PIRQ[H]#/GPIO[5] PLOCK# PWROK RCIN# REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[A]#/GPIO[0] REQ[B]#/REQ[5]#/GPIO[1] RESERVED1
Signal Name RESERVED2 RI# RSM_PWROK RSMRST# RTCRST# RTCX1 RTCX2 SDA[0] SDA[1] SDA[2] SDCS1# SDCS3# SDD[0] SDD[1] SDD[2] SDD[3] SDD[4] SDD[5] SDD[6] SDD[7] SDD[8] SDD[9] SDD[10] SDD[11] SDD[12] SDD[13] SDD[14] SDD[15] SDDACK# SDDREQ SDIOR# (/SDWSTB/ SRDMARDY#) SDIOW# (/SDSTOP) SERIRQ SERR# SIORDY (/SDRSTB/ SWDMARDY#) SIU_LAD[0]
Advance Information Datasheet
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Intel(R) 82801E C-ICH
Table 5.
Ball List By Signal Name
Ball Number A15 C14 E14 E13 C15 B15 D13 A14 D17 B20 D18 B19 A21 E16 E17 D19 D16 C16 A18 B16 D15 A16 B18 C17 U1 T2 R4 T21 Y5 AA4 AB10 D4 T22 U3 A11 A12 AA5 AC2
Table 5.
Ball List By Signal Name
Ball Number AB2 E4 A19 T5 U4 V2 W1 V21 W22 AB1 AC10 D11 V5 Y3 AB6 B8 B14 B22 E2 F8 F9 F10 F14 F21 F23 H22 J18 K10 K12 K14 K18 L14 M10 M14 N5 P10 P12 P14
Signal Name SIU_LAD[1] SIU_LAD[2] SIU_LAD[3] SIU_LCLK SIU_LDRQ# SIU_LFRAME# SIU_RESET# SIU_SERIRQ SIU0_CTS# SIU0_DCD# SIU0_DSR# SIU0_DTR# SIU0_RI# SIU0_RTS# SIU0_RXD SIU0_TXD SIU1_CTS# SIU1_DCD# SIU1_DSR# SIU1_DTR# SIU1_RI# SIU1_RTS# SIU1_RXD SIU1_TXD SMBALERT#/GPIO[11] SMBCLK SMBDATA SMI# SMLINK[0] SMLINK[1] SPKR STOP# STPCLK# SUSCLK THRM# TP[0] TP[1] TP[2]
Signal Name TP[3] TRDY# UART_CLK USBP0N USBP0P USBP1N USBP1P V_CPU_IO V_CPU_IO V5REF V5REF V5REF V5REF V5REF VBIAS Vcc1_8 Vcc1_8 Vcc1_8 Vcc1_8 Vcc1_8 Vcc1_8 Vcc1_8 Vcc1_8 Vcc1_8 Vcc1_8 Vcc1_8 Vcc1_8 Vcc1_8 Vcc1_8 Vcc1_8 Vcc1_8 Vcc1_8 Vcc1_8 Vcc1_8 Vcc1_8 Vcc1_8 Vcc1_8 Vcc1_8
20
Advance Information Datasheet
Intel(R) 82801E C-ICH
Table 5.
Ball List By Signal Name
Ball Number P18 R18 T18 AB3 AB21 B17 C18 E6 E18 F6 F7 F15 F16 F17 F18 G6 G18 H6 H18 J6 K6 P6 R3 R6 T6 U6 U18 V3 V6 V7 V8 V9 V10 V14 V15 V16 V17 V18
Table 5.
Ball List By Signal Name
Ball Number W10 W8 AA8 W21 A1 A6 A9 A13 A17 A20 A23 C4 C6 C12 C19 D1 D9 D22 E5 E7 E15 E19 G3 G22 H23 J1 J5 J19 J20 J21 J22 K11 K13 K21 K23 L3 L10 L11
Signal Name Vcc1_8 Vcc1_8 Vcc1_8 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3
Signal Name Vcc3_3 VccRTC VccRTC VRMPWRGD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Advance Information Datasheet
21
Intel(R) 82801E C-ICH
Table 5.
Ball List By Signal Name
Ball Number L12 L13 L20 L22 M11 M12 M13 M21 M23 N1 N10 N11 N12 N13 N14 N20 N22 P5 P11 P13 P21 P23 R20
Table 5.
Ball List By Signal Name
Ball Number R21 R22 T1 U5 W5 W6 Y1 Y6 AA2 AA3 AA12 AA16 AA20 AA22 AB7 AC1 AC3 AC4 AC5 AC6 AC8 AC13 AC23
Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
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Advance Information Datasheet
Intel(R) 82801E C-ICH
2.2
Mechanical Specifications
Figure 4. Intel(R) 82801E C-ICH Package (Top View)
Notes: 1. All Dimensions and tolerances conform to ANSI Y14.5M - 1982 2. All Dimensions are in millimeters.
Advance Information Datasheet
23
Intel(R) 82801E C-ICH
Figure 5. Intel(R) 82801E C-ICH Package (Side View)
Notes: 1. All Dimensions and tolerances conform to ANSI Y14.5M - 1982 2. All Dimensions are in millimeters. 3. Primary datum -C- and seating plane are defined by the spherical crowns of the solder balls.
Figure 6. Intel(R) 82801E C-ICH Package (Bottom View)
Notes: 1. All Dimensions and tolerances conform to ANSI Y14.5M - 1982 2. Dimension is measured at the maximum solder ball diameter. Parallel to Datum -C- on side view illustration. 3. All Dimensions are in millimeters.
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Advance Information Datasheet
Intel(R) 82801E C-ICH
3.0
Signal Descriptions
This section provides a detailed description of each signal. The signals are arranged in functional groups according to their associated interface. The "#" symbol at the end of the signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. When "#" is not present, the signal is asserted when at the high voltage level. The following notations are used to describe the signal type:
I O OD I/O Input pin Output pin Open drain output pin. Bidirectional input/output pin.
3.1
Table 6.
Alphabetical Signal Reference
82801E C-ICH Signal Description (Sheet 1 of 11)
Signal A20GATE Type I Description A20 Gate: This signal is from the keyboard controller. It acts as an alternative method to force the A20M# signal active. A20GATE eliminates the need for the external OR gate needed with various other PCIsets. Mask A20: A20M# goes active based on setting the appropriate bit in the Port 92h register, or based on the A20GATE signal. Speed Strap: During the reset sequence, 82801E C-ICH drives A20M# high if the corresponding bit is set in the FREQ_STRP register. PCI Address/Data: AD[31:0] is a multiplexed address and data bus. During the first clock of a transaction, AD[31:0] contain a physical address (32 bits). During subsequent clocks, AD[31:0] contain data. The 82801E C-ICH drives all 0s on AD[31:0] during the address phase of all PCI Special Cycles. APIC Clock: The APIC clock runs at 33.333 MHz. APIC Data: These bidirectional open drain signals are used to send and receive data over the APIC bus. As inputs, the data is valid on the rising edge of APICCLK. As outputs, new data is driven from the rising edge of the APICCLK.
A20M#
O
AD[31:0]
I/O
APICCLK
I
APICD[1:0]
I/OD
Advance Information Datasheet
25
Intel(R) 82801E C-ICH
Table 6.
82801E C-ICH Signal Description (Sheet 2 of 11)
Signal Type Description Bus Command and Byte Enables: The command and byte enable signals are multiplexed on the same PCI pins. During the address phase of a transaction, C/BE[3:0]# define the bus command. During the data phase, C/BE[3:0]# define the Byte Enables. C/BE[3:0]# 0000 0001 0010 0011 0110 C/BE[3:0]# I/O 0111 1010 1011 1100 1101 1110 1111 Command Type Interrupt Acknowledge Special Cycle I/O Read I/O Write Memory Read Memory Write Configuration Read Configuration Write Memory Read Multiple DAC Mode Address to be latched (target only) Memory Read Line Memory Write and Invalidate
All command encodings not shown are reserved. The 82801E C-ICH does not decode reserved values, and therefore will not respond when a PCI master generates a cycle using one of the reserved values. As a target, the 82801E C-ICH can support DAC mode addressing for 44 bits. CLK14 CLK48 CLK66 (HLCLK) I I I Oscillator Clock: CLK14 is used for 8254 timers and runs at 14.31818 MHz. 48 MHz Clock: CLK48 is used to for the USB controller and runs at 48 MHz. 66 MHz Clock (HLCLK): CLK66 is used for the hub interface and runs at 66 MHz. Processor Power Good: This signal should be connected to the processor's PWRGOOD input. This is an open-drain output signal (external pull-up resistor required) that represents a logical AND of the 82801E C-ICH's PWROK and VRMPWRGD signals. Processor Sleep: This signal puts the processor into a state that saves substantial power compared to Stop-Grant state. However, during that time, no snoops occur. NOTE: The 82801E C-ICH does not support Sleep states. This signal must be pulled up through an 8.2 K resistor to 3.3 V. Device Select: The 82801E C-ICH asserts DEVSEL# to claim a PCI transaction. As an output, the 82801E C-ICH asserts DEVSEL# when a PCI master peripheral attempts an access to an internal 82801E C-ICH address or an address destined for the hub interface (main memory or AGP). As an input, DEVSEL# indicates the response to an 82801E C-ICH-initiated transaction on the PCI bus. DEVSEL# is tri-stated from the leading edge of PCIRST#. DEVSEL# remains tri-stated by the 82801E C-ICH until driven by a target device. EEPROM Chip Select: These signals are chip-select signals to the EEPROMs. EEPROM Data In: These signals transfer data from the EEPROMs to the 82801E C-ICH. These signals have an integrated pull-up resistor. EEPROM Data Out: These signals transfer data from the 82801E C-ICH to the EEPROMs. EEPROM Shift Clock: These signals are the serial shift clock output to the EEPROMs.
CPUPWRGD
OD
CPUSLP#
O
DEVSEL#
I/O
EE0_CS EE1_CS EE0_DIN EE1_DIN EE0_DOUT EE1_DOUT EE0_SHCLK EE1_SHCLK
O I O O
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Advance Information Datasheet
Intel(R) 82801E C-ICH
Table 6.
82801E C-ICH Signal Description (Sheet 3 of 11)
Signal Type Description Numeric Coprocessor Error: This signal is tied to the coprocessor error signal on the processor. FERR# is only used if the 82801E C-ICH coprocessor error reporting function is enabled in the General Control Register (Device 31:Function 0, Offset D0, bit 13). If FERR# is asserted, the 82801E C-ICH generates an internal IRQ13 to its interrupt controller unit. It is also used to gate the IGNNE# signal to ensure that IGNNE# is not asserted to the processor unless FERR# is active. FERR# requires an external weak pull-up to ensure a high level when the coprocessor error function is disabled. Cycle Frame: The current Initiator asserts FRAME# to indicate the beginning and duration of a PCI transaction. While the initiator asserts FRAME#, data transfers continue. When the initiator deasserts FRAME#, the transaction is in the final data phase. FRAME# is an input to the 82801E C-ICH when the 82801E C-ICH is the target, and FRAME# is an output from the 82801E C-ICH when the 82801E C-ICH is the Initiator. FRAME# remains tri-stated by the 82801E C-ICH until driven by an Initiator. Firmware Hub Signals: These signals are muxed with LPC address signals. Firmware Hub Signals: This signal is muxed with the LPC LFRAME# signal. PCI Grants: The 82801E C-ICH supports up to four masters on the PCI bus. GNT[5]# is muxed with PC/PCI GNT[B]# (must choose one or the other, but not both). If not needed for PCI or PC/PCI, GNT[5]# can instead be used as a GPIO. Pull-up resistors are not required on these signals. If pullups are used, they should be tied to the Vcc3_3 power rail. GNT[B]#/GNT[5]#/GPIO[17] has an internal pull-up. PC/PCI DMA Acknowledges [A:B]: This grant serializes an ISA-like DACK# for the purpose of running DMA/ISA master cycles over the PCI bus. This is used by devices such as PCI-based Super I/O or audio codecs which need to perform legacy 8237 DMA but have no ISA bus. When not used for PC/PCI, these signals can be used as General Purpose Outputs. GNTB# can also be used as the fourth PCI bus master grant output. These signal have internal pull-up resistors. I Fixed as Input only. Main Power Well. Can instead be used for PC/PCI REQ[A:B]#. GPIO[1] can also alternatively be used for PCI REQ[5]#. Not implemented. I I I I I I I I O O O OD O Fixed as Input only. Main power well. Can be used instead as PIRQ[G:H]#. Fixed as Input only. Main power well. Fixed as Input only. Main power well. Not muxed. Fixed as Input only. Main power well. Not muxed. Not implemented. Fixed as Input only. Main power well. Can instead be used for SMBALERT#. Fixed as Input only. Main power well. Not muxed. Not implemented. Fixed as Output only. Main Power Well. Can instead be used for PC/PCI GNT[A:B]#. GPIO[17] can also alternatively be used for PCI GNT[5]#. Integrated pull-up resistor. Fixed as Output only. Main power well. Fixed as Output only. Main power well. Fixed as Output only. Main power well. Open-drain output. Fixed as Output only. Main power well.
FERR#
I
FRAME#
I/O
FWH[3:0] /LAD[3:0] FWH[4] /LFRAME#
I/O I/O
GNT[3:0]# GNT[5]# /GNT[B]# /GPIO[17]# O
GNT[A]# /GPIO[16] /GNT[B]# /GNT[5]# /GPIO[17] O
GPIO[1:0] GPIO[3:2] GPIO[5:4] GPIO[6] GPIO[7] GPIO[8] GPIO[10:9] GPIO[11] GPIO[13:12] GPIO[15:14] GPIO[17:16] GPIO[20:18] GPIO[21] GPIO[22] GPIO[23]
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Intel(R) 82801E C-ICH
Table 6.
82801E C-ICH Signal Description (Sheet 4 of 11)
Signal GPIO[24] GPIO[25] GPIO[26] GPIO[28:27] GPIO[31:29] HL[11:0] HL_STB HL_STB# HLCOMP HUBREF Type I/O I/O I/O I/O O I/O I/O I/O I/O Description Can be input or output. Main power well. Can be input or output. Main power well. Not Muxed. Not implemented. Can be input or output. Main power well. Unmuxed. Not implemented. Hub Interface Signals Hub Interface Strobe: One of two differential strobe signals used to transmit and receive data through the hub interface. Hub Interface Strobe Complement: Second of the two differential strobe signals. Hub Interface Compensation: Used for hub interface buffer compensation. 0.9 V reference for the hub interface. Ignore Numeric Error: This signal is connected to the ignore error pin on the processor. IGNNE# is only used if the 82801E C-ICH coprocessor error reporting function is enabled in the General Control Register (Device 31:Function 0, Offset D0, bit 13). When FERR# is active, indicating a coprocessor error, a write to the Coprocessor Error Register (F0h) causes the IGNNE# to be asserted. IGNNE# remains asserted until FERR# is negated. If FERR# is not asserted when the Coprocessor Error Register is written, the IGNNE# signal is not asserted. Speed Strap: During the reset sequence, 82801E C-ICH drives IGNNE# high if the corresponding bit is set in the FREQ_STRP register. INIT# O Initialization: INIT# is asserted by the 82801E C-ICH for 16 PCI clocks to reset the processor. 82801E C-ICH can be configured to support processor BIST. In that case, INIT# will be active when PCIRST# is active. Processor Interrupt: INTR is asserted by the 82801E C-ICH to signal the processor that an interrupt request is pending and needs to be serviced. It is an asynchronous output and normally driven low. Speed Strap: During the reset sequence, 82801E C-ICH drives INTR high if the corresponding bit is set in the FREQ_STRP register. INTRUDER# I Intruder Detect: This signal can be set to disable system if box detected open. This signal's status is readable, so it can be used like a GPI if the Intruder Detection is not needed. Initiator Ready: IRDY# indicates the 82801E C-ICH's ability, as an Initiator, to complete the current data phase of the transaction. It is used in conjunction with TRDY#. A data phase is completed on any clock both IRDY# and TRDY# are sampled asserted. During a write, IRDY# indicates the 82801E C-ICH has valid data present on AD[31:0]. During a read, it indicates the 82801E C-ICH is prepared to latch data. IRDY# is an input to the 82801E C-ICH when the 82801E C-ICH is the Target and an output from the 82801E C-ICH when the 82801E C-ICH is an Initiator. IRDY# remains tri-stated by the 82801E C-ICH until driven by an Initiator. Interrupt Request 14:15: These interrupt inputs are connected to the IDE drives. IRQ14 is used by the drives connected to the primary controller and IRQ15 is used by the drives connected to the secondary controller. LPC Multiplexed Command, Address, Data: Internal pull-ups are provided. LAN Interface Clock: This signal is driven by the LAN Connect component. The frequency range is 0.8 MHz to 50 MHz. LAN Reset/Sync: The LAN Connect component's Reset and Sync signals are multiplexed onto this pin.
IGNNE#
O
INTR
O
IRDY#
I/O
IRQ[14:15] LAD[3:0] /FWH[3:0] LAN0_CLK LAN1_CLK LAN0_RSTSYNC LAN1_RSTSYNC
I
I/O I O
28
Advance Information Datasheet
Intel(R) 82801E C-ICH
Table 6.
82801E C-ICH Signal Description (Sheet 5 of 11)
Signal LAN0_RXD[2:0] LAN1_RXD[2:0] LAN0_TXD[2:0] LAN1_TXD[2:0] LDRQ[1:0]# LFRAME# /FWH[4] NC[10:1] Type I Description Received Data: The LAN Connect component uses these signals to transfer data and control information to the integrated LAN Controller. These signals have integrated weak pull-up resistors. Transmit Data: The integrated LAN Controller uses these signals to transfer data and control information to the LAN Connect component. LPC Serial DMA/Master Request Inputs: These signals are used to request DMA or bus master access. Typically, they are connected to external Super I/O device. An internal pull-up resistor is provided on these signals. LPC Frame: LFRAME# indicates the start of an LPC cycle, or an abort. No Connect. Do not connect these pins. -- Optional: NC[10:6, 3:1] can be routed to a test point for use in manufacturing NAND tree testing. Non-Maskable Interrupt: NMI is used to force a non-maskable interrupt to the processor. The 82801E C-ICH can generate an NMI when either SERR# or IOCHK# is asserted. The processor detects an NMI when it detects a rising edge on NMI. NMI is reset by setting the corresponding NMI source enable/disable bit in the NMI Status and Control Register. Speed Strap: During the reset sequence, 82801E C-ICH drives NMI high if the corresponding bit is set in the FREQ_STRP register. OC[1:0]# I Overcurrent Indicators: These signals set corresponding bits in the USB controllers to indicate that an overcurrent condition has occurred. Calculated/Checked Parity: PAR uses "even" parity calculated on 36 bits, AD[31:0] plus C/BE[3:0]#. "Even" parity means that the 82801E C-ICH counts the number of 1s within the 36 bits plus PAR and the sum is always even. The 82801E C-ICH always calculates PAR on 36 bits, regardless of the valid byte enables. The 82801E C-ICH generates PAR for address and data phases and only guarantees PAR to be valid one PCI clock after the corresponding address or data phase. The 82801E C-ICH drives and tri-states PAR identically to the AD[31:0] lines except that the 82801E C-ICH delays PAR by exactly one PCI clock. PAR is an output during the address phase (delayed one clock) for all 82801E C-ICH initiated transactions. PAR is an output during the data phase (delayed one clock) when the 82801E C-ICH is the Initiator of a PCI write transaction, and when it is the target of a read transaction. 82801E C-ICH checks parity when it is the target of a PCI write transaction. If a parity error is detected, the 82801E C-ICH sets the appropriate internal status bits, and has the option to generate an NMI# or SMI#. PCI Clock: This is a 33 MHz clock. PCICLK provides timing for all transactions on the PCI Bus. PCI Reset: 82801E C-ICH asserts PCIRST# to reset devices that reside on the PCI bus. The 82801E C-ICH asserts PCIRST# during power-up and when S/W initiates a hard reset sequence through the RC (CF9h) register. The 82801E C-ICH drives PCIRST# inactive a minimum of 1 ms after PWROK is driven active. The 82801E C-ICH drives PCIRST# active a minimum of 1 ms when initiated through the RC register. Primary IDE Device Address: These output signals are connected to the corresponding signals on the primary IDE connector. They are used to indicate which byte in either the ATA command block or control block is being addressed. Primary IDE Device Chip Selects for 100 Range: This signal is for the ATA command register block. This output signal is connected to the corresponding signal on the primary IDE connector.
O
I
O
NMI
O
PAR
I/O
PCICLK
I
PCIRST#
O
PDA[2:0]
O
PDCS1#
O
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Intel(R) 82801E C-ICH
Table 6.
82801E C-ICH Signal Description (Sheet 6 of 11)
Signal PDCS3# Type O Description Primary IDE Device Chip Select for 300 Range: This signal is for the ATA control register block. This output signal is connected to the corresponding signal on the primary IDE connector. Primary IDE Device Data: These signals directly drive the corresponding signals on the primary IDE connector. There is a weak internal pull-down resistor on PDD[7]. Primary IDE Device DMA Acknowledge: This signal directly drives the DAK# signal on the primary IDE connector. This signal is asserted by the 82801E C-ICH to indicate to the IDE DMA slave device that a given data transfer cycle (assertion of DIOR# or DIOW#) is a DMA data transfer cycle. This signal is used in conjunction with the PCI bus master IDE function and is not associated with any AT-compatible DMA channel. Primary IDE Device DMA Request: This input signal is directly driven from the DRQ signal on the primary IDE connector. It is asserted by the IDE device to request a data transfer, and used in conjunction with the PCI bus master IDE function. This signal is not associated with any AT-compatible DMA channel. There is a weak internal pull-down resistor on PDDREQ. Primary Disk I/O Read (PIO and Non-Ultra DMA): This is the command to the IDE device that it may drive data on the PDD lines. Data is latched by the 82801E C-ICH on the deassertion edge of PDIOR#. The IDE device is selected either by the ATA register file chip selects (PDCS1#, PDCS3#) and the PDA lines, or the IDE DMA acknowledge (PDDAK#). O Primary Disk Write Strobe (Ultra DMA Writes to Disk): PDWSTB is the data write strobe for writes to disk. When writing to disk, the 82801E C-ICH drives valid data on rising and falling edges of PDWSTB. Primary Disk DMA Ready (Ultra DMA Reads from Disk): PRDMARDY# is the DMA ready for reads from disk. When reading from disk, the 82801E C-ICH deasserts PRDMARDY# to pause burst data transfers. Primary Disk I/O Write (PIO and Non-Ultra DMA): This is the command to the IDE device that it may latch data from the PDD lines. Data is latched by the IDE device on the deassertion edge of PDIOW#. The IDE device is selected either by the ATA register file chip selects (PDCS1#, PDCS3#) and the PDA lines, or the IDE DMA acknowledge (PDDAK#). Primary Disk Stop (Ultra DMA): 82801E C-ICH asserts PDSTOP to terminate a burst. Parity Error: An external PCI device drives PERR# when it receives data that has a parity error. The 82801E C-ICH drives PERR# when it detects a parity error. The ICH can either generate an NMI# or SMI# upon detecting a parity error (either detected internally or reported via the PERR# signal). Primary I/O Channel Ready (PIO): This signal keeps the strobe active (PDIOR# on reads, PDIOW# on writes) longer than the minimum width. It adds wait states to PIO transfers. PIORDY /(PDRSTB /PWDMARDY#) I Primary Disk Read Strobe (Ultra DMA Reads from Disk): When reading from disk, the 82801E C-ICH latches data from the disk on rising and falling edges of PDRSTB. Primary Disk DMA Ready (Ultra DMA Writes to Disk): When writing to disk, PWDMARDY# is deasserted by the disk to pause burst data transfers. PCI Interrupt Requests: In Non-APIC Mode the PIRQx# signals can be routed to interrupts 3:7, 9:12, 14, or 15 as described in the Interrupt Steering section. Each PIRQx# line has a separate Route Control Register. In APIC mode, these signals are connected to the internal I/O APIC in the following fashion: PIRQ[A]# is connected to IRQ16, PIRQ[B]# to IRQ17, PIRQ[C]# to IRQ18, and PIRQ[D]# to IRQ19. This frees the ISA interrupts.
PDD[15:0]
I/O
PDDACK#
O
PDDREQ
I
PDIOR# /(PDWSTB /PRDMARDY#)
PDIOW# /(PDSTOP)
O
PERR#
I/O
PIRQ[A:D]#
I/OD
30
Advance Information Datasheet
Intel(R) 82801E C-ICH
Table 6.
82801E C-ICH Signal Description (Sheet 7 of 11)
Signal Type Description PCI Interrupt Requests: In Non-APIC Mode the PIRQx# signals can be routed to interrupts 3:7, 9:12, 14 or 15 as described in the Interrupt Steering section. Each PIRQx# line has a separate Route Control Register. I/OD In APIC mode, these signals are connected to the internal I/O APIC in the following fashion: PIRQ[E]# is connected to IRQ20, PIRQ[F]# to IRQ21, PIRQ[G]# to IRQ22, and PIRQ[H]# to IRQ23. If not needed for interrupts, these signals can be used as GPIO. PCI Lock: PLOCK# indicates an exclusive bus operation and may require multiple transactions to complete. 82801E C-ICH asserts PLOCK# when it performs non-exclusive transactions on the PCI bus. Power OK: When asserted, PWROK is an indication to the 82801E C-ICH that core power and PCICLK have been stable for at least 1 ms. PWROK can be driven asynchronously. When PWROK is negated, the 82801E C-ICH asserts PCIRST#. Keyboard Controller Reset Processor: The keyboard controller can generate INIT# to the processor. This saves the external OR gate with the 82801E C-ICH's other sources of INIT#. When the 82801E C-ICH detects the assertion of this signal, INIT# is generated for 16 PCI clocks. PCI Requests: The 82801E C-ICH supports up to four masters on the PCI bus. REQ[5]# is muxed with PC/PCI REQ[B]# (must choose one or the other, but not both). If not used for PCI or PC/PCI, REQ[5]#/REQ[B]# can instead be used as GPIO[1]. NOTE: REQ[0]# is programmable to have improved arbitration latency for supporting PCI-based 1394 controllers. PC/PCI DMA Request [A:B]: This request serializes ISA-like DMA Requests for the purpose of running ISA-compatible DMA cycles over the PCI bus. This is used by devices such as PCI-based Super I/O or audio codecs that need to perform legacy 8237 DMA but have no ISA bus. When not used for PC/PCI requests, these signals can be used as General Purpose Inputs. Instead, REQ[B]# can be used as the fourth PCI bus request. -- I This signal must have an external pull up to Vcc3_3. Ring Indicate: From the modem interface. This signal can be enabled as a wake event; this is preserved across power failures. Resume Well Power OK: When asserted, this signal is an indication to the 82801E C-ICH that the resume well power has been stable for at least 10 ms. NOTE: The 82801E C-ICH does not use the Resume Well Power OK signal. RSMRST# I Resume Well Reset: RSMRST# is used for resetting the resume power plane logic. NOTE: The 82801E C-ICH does not use the Resume Well Reset signal. RTC Reset: When asserted, this signal resets register bits in the RTC well and sets the RTC_PWR_STS bit (bit 2 in GEN_PMCON3 register). This signal is also used to enter the test modes documented in "Test Signals" on page 49. NOTE: Clearing CMOS in an 82801E C-ICH-based platform can be done by using a jumper on RTCRST# or GPI, or using SAFEMODE strap. Implementations should not attempt to clear CMOS by using a jumper to pull VccRTC low. Crystal Input 1: This signal is connected to the 32.768 KHz crystal. If no external crystal is used, then RTCX1 can be driven with the desired clock rate. Crystal Input 2: This signal is connected to the 32.768 KHz crystal. If no external crystal is used, then RTCX2 should be left floating.
PIRQ[E:F]# PIRQ[G]#/GPIO[4] PIRQ[H]#/GPIO[5]
PLOCK#
I/O
PWROK
I
RCIN#
I
REQ[3:0]# REQ[5]# /REQ[B]# /GPIO[1] I
REQ[A]# /GPIO[0] REQ[B]# /REQ[5]# /GPIO[1] RESERVED1 RESERVED2 RI# I
RSM_PWROK
I
RTCRST#
I
RTCX1
Special
RTCX2
Special
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Intel(R) 82801E C-ICH
Table 6.
82801E C-ICH Signal Description (Sheet 8 of 11)
Signal Type Description Secondary IDE Device Address: These output signals are connected to the corresponding signals on the secondary IDE connectors. They are used to indicate which byte in either the ATA command block or control block is being addressed. Secondary IDE Device Chip Selects for 100 Range: This signal is for the ATA command register block. This output signal is connected to the corresponding signal on the secondary IDE connector. Secondary IDE Device Chip Select for 300 Range: This signal is for the ATA control register block. This output signal is connected to the corresponding signal on the secondary IDE connector. Secondary IDE Device Data: These signals directly drive the corresponding signals on the secondary IDE connector. There is a weak internal pull-down resistor on SDD[7]. Secondary IDE Device DMA Acknowledge: This signal directly drives the DAK# signal on the secondary IDE connectors. This signal is asserted by the 82801E C-ICH to indicate to the IDE DMA slave device that a given data transfer cycle (assertion of DIOR# or DIOW#) is a DMA data transfer cycle. This signal is used in conjunction with the PCI bus master IDE function and is not associated with any AT-compatible DMA channel. Secondary IDE Device DMA Request: This input signal is directly driven from the DRQ signals on the secondary IDE connector. It is asserted by the IDE device to request a data transfer, and used in conjunction with the PCI bus master IDE function. It is not associated with any AT-compatible DMA channel. There is a weak internal pull-down resistor on SDDREQ. Secondary Disk I/O Read (PIO and Non-Ultra DMA): This is the command to the IDE device that it may drive data on the SDD lines. Data is latched by the 82801E C-ICH on the deassertion edge of SDIOR#. The IDE device is selected either by the ATA register file chip selects (SDCS1# or SDCS3#) and the SDA lines, or the IDE DMA acknowledge (SDDAK#). O Secondary Disk Write Strobe (Ultra DMA Writes to Disk): This is the data write strobe for writes to disk. When writing to disk, the 82801E C-ICH drives valid data on rising and falling edges of SDWSTB. Secondary Disk DMA Ready (Ultra DMA Reads from Disk): This is the DMA ready for reads from disk. When reading from disk, the 82801E C-ICH deasserts SRDMARDY# to pause burst data transfers. Secondary Disk I/O Write (PIO and Non-Ultra DMA): This is the command to the IDE device that it may latch data from the SDD lines. Data is latched by the IDE device on the deassertion edge of SDIOW#. The IDE device is selected either by the ATA register file chip selects (SDCS1# or SDCS3#) and the SDA lines, or the IDE DMA acknowledge (SDDAK#). Secondary Disk Stop (Ultra DMA): The 82801E C-ICH asserts SDSTOP to terminate a burst. SERIRQ SERR# I/O I Serial Interrupt Request: This pin implements the serial interrupt protocol. System Error: SERR# can be pulsed active by any PCI device that detects a system error condition. Upon sampling SERR# active, the 82801E C-ICH has the ability to generate an NMI, SMI#, or interrupt. Secondary I/O Channel Ready (PIO): This signal keeps the strobe active (SDIOR# on reads, SDIOW# on writes) longer than the minimum width. It adds wait states to SIO transfers. SIORDY /(SDRSTB /SWDMARDY#) I Secondary Disk Read Strobe (Ultra DMA Reads from Disk): When reading from disk, the 82801E C-ICH latches data from the disk on rising and falling edges of SDRSTB. Secondary Disk DMA Ready (Ultra DMA Writes to Disk): When writing to disk, SWDMARDY# is deasserted by the disk to pause burst data transfers.
SDA[2:0]
O
SDCS1#
O
SDCS3#
O
SDD[15:0]
I/O
SDDACK#
O
SDDREQ
I
SDIOR# /(SDWSTB/ SRDMARDY#)
SDIOW# /(SDSTOP)
O
32
Advance Information Datasheet
Intel(R) 82801E C-ICH
Table 6.
82801E C-ICH Signal Description (Sheet 9 of 11)
Signal SIU_LAD[3:0] SIU_LCLK SIU_LDRQ# SIU_LFRAME# SIU_RESET# SIU_SERIRQ Type I/O I O I I I/O Description SIU LPC Multiplexed Command, Address, Data: Internal pull-ups are provided. SIU LPC clock input to SIU: 33 MHz LPC clock. SIU LPC Serial DMA/Master Request Output: Used by SIU devices to indicate a DMA request. These signals have weak internal pull-up resistors to avoid external glue. SIU LPC Frame: Indicates the start of an LPC cycle, or an abort. SIU Reset: This signal should be tied to PCI RESET. SIU Serial IRQ input: This pin receives the serial interrupt protocol from external devices. Pull up if unused. Clear To Send: Active low, this pin indicates that data can be exchanged between CICH and external interface. These pins have no effect on the transmitter. SIU0_CTS# SIU1_CTS# I NOTE: These pins could be used as Modem Status Input whose condition can be tested by the processor by reading bit 4 (CTS) of the Modem Status register (MSR). Bit 4 is the complement of the CTS# signal. Bit 0 (DCTS) of the MSR indicates whether the CTS# input has changed state since the previous reading of the MSR. When the CTS bit of the MSR changes state an interrupt is generated if the Modem Status Interrupt is enabled. Data Carrier Detect for UART0 and UART1: Active low, this pin indicates that data carrier has been detected by the external agent. SIU0_DCD# SIU1_DCD# NOTE: These pins are Modem Status Inputs whose condition can be tested by the processor by reading bit 7 (DCD) of the Modem Status register (MSR). Bit 7 is the complement of the DCD# signal. Bit 3 (DDCD) of the MSR indicates whether the DCD# input has changed state since the previous reading of the MSR. When the DCD bit of the MSR changes state an interrupt is generated if the Modem Status Interrupt is enabled. Data Set Ready for UART0 and UART1: Active low, this pin indicates that the external agent is ready to communicate with 82801E C-ICH UARTs. These pins have no effect on the transmitter. SIU0_DSR# SIU1_DSR# I NOTE: These pins could be used as Modem Status Inputs whose condition can be tested by the processor by reading bit 5 (DSR) of the Modem Status register. Bit 5 is the complement of the DSR# signal. Bit 1 (DDSR) of the Modem status register (MSR) indicates whether the DSR# input has changed state since the previous reading of the MSR. When the DSR bit of the MSR changes state an interrupt is generated if the Modem Status Interrupt is enabled. Data Terminal Ready for UART0 and UART1: When low these pins informs the modem or data set that CICH UART 0, 1 are ready to establish a communication link. The DTR#x(x=0,1) output signals can be set to an active low by programming the DTRx (x-0,1) (bit0) of the Modem control register to a logic `1'. A Reset operation sets this signal to its inactive state (logic `1'). LOOP mode operation holds this signal in its inactive state. Ring Indicator for UART0 and UART1: Active low, this pin indicates that a telephone ringing signal has been received by the external agent. SIU0_RI# SIU1_RI# NOTE: These pins are Modem Status Input whose condition can be tested by the processor by reading bit 6 (RI) of the Modem Status register (MSR). Bit 6 is the complement of the RI# signal. Bit 2 (TERI) of the MSR indicates whether the DCD# input has changed state since the previous reading of the MSR. When the RI bit of the MSR changes state an interrupt is generated if the Modem Status Interrupt is enabled.
I
SIU0_DTR# SIU1_DTR#
O
I
Advance Information Datasheet
33
Intel(R) 82801E C-ICH
Table 6.
82801E C-ICH Signal Description (Sheet 10 of 11)
Signal Type Description Request To Send for UART0 and UART1: When low these pins informs the modem or data set that CICH UART 0, 1 are ready to establish a communication link. The RTS#x(x=0,1) output signals can be set to an active low by programming the RTSx (x-0,1) (bit1) of the Modem control register to a logic `1'. A Reset operation sets this signal to its inactive state (logic `1'). LOOP mode operation holds this signal in its inactive state. Serial Input for UART0 and UART1: Serial data input from device pin to the receive port. Serial Output for UART0 and UART1: Serial data output to the communication peripheral/modem or data set. Upon reset, the TXD pins will be set to MARKING condition (logic `1' state). SMBus Alert: This signal is used to wake the system or generate an SMI#. If not used for SMBALERT#, it can be used as a GPI. SMBus Clock: External pull-up is required. SMBus Data: External pull-up is required. System Management Interrupt: SMI# is an active low output synchronous to PCICLK. It is asserted by the 82801E C-ICH in response to one of many enabled hardware or software events. System Management Link: These signals are an SMBus link to an optional external system management ASIC or LAN controller. External pull-ups are required. NOTE: SMLINK[0] corresponds to an SMBus Clock signal and SMLINK[1] corresponds to an SMBus Data signal. Speaker: The SPKR signal is the output of counter 2 and is internally ANDed with Port 61h bit 1 to provide Speaker Data Enable. This signal drives an external speaker driver device, which in turn drives the system speaker. Upon PCIRST#, its output state is 1. NOTE: SPKR is sampled at the rising edge of PWROK as a functional strap. See "Functional Straps" on page 49 for more details. Stop: STOP# indicates that the 82801E C-ICH, as a Target, is requesting the Initiator to stop the current transaction. STOP# causes the 82801E C-ICH, as an Initiator, to stop the current transaction. STOP# is an output when the 82801E C-ICH is a target and an input when the 82801E C-ICH is an Initiator. STOP# is tri-stated from the leading edge of PCIRST#. STOP# remains tri-stated until driven by the 82801E C-ICH. Stop Clock Request: STPCLK# is an active low output synchronous to PCICLK. It is asserted by the 82801E C-ICH in response to one of many hardware or software events. When the processor samples STPCLK# asserted, it responds by stopping its internal clock. Suspend Clock: This signal is an output of the RTC generator circuit and is used by other chips for the refresh clock. Thermal Alarm: THRM# is an active low signal generated by external hardware to start the hardware clock throttling mode. This signal can also generate an SMI# or an SCI. Test Points: TP0: This signal must have an external pull-up to Vcc3_3. TP[3:0] I TP1: Route to a test point with option to jumper to Vcc1_8. Used for NAND tree testing. Otherwise jumper to Vcc1_8. TP2 and TP3: Route to a test point with option to jumper to VSS. Used for NAND tree testing. Otherwise jumper to VSS.
SIU0_RTS# SIU1_RTS#
O
SIU0_RXD SIU1_RXD SIU0_TXD SIU1_TXD SMBALERT# /GPIO[11] SMBCLK SMBDATA SMI#
I
O
I I/OD I/OD O
SMLINK[1:0]
I/OD
SPKR
O
STOP#
I/O
STPCLK#
O
SUSCLK
O
THRM#
I
34
Advance Information Datasheet
Intel(R) 82801E C-ICH
Table 6.
82801E C-ICH Signal Description (Sheet 11 of 11)
Signal Type Description Target Ready: TRDY# indicates the 82801E C-ICH's ability as a Target to complete the current data phase of the transaction. TRDY# is used in conjunction with IRDY#. A data phase is completed when both TRDY# and IRDY# are sampled asserted. During a read, TRDY# indicates that the 82801E C-ICH, as a Target, has placed valid data on AD[31:0]. During a write, TRDY# indicates the 82801E C-ICH, as a Target is prepared to latch data. TRDY# is an input to the 82801E C-ICH when the 82801E C-ICH is the Initiator and an output from the 82801E C-ICH when the 82801E C-ICH is a Target. TRDY# is tri-stated from the leading edge of PCIRST#. TRDY# remains tri-stated by the 82801E C-ICH until driven by a target. Input clock to the SIU. This clock is passed to the baud clock generation logic of each UART in the SIU.
TRDY#
I/O
UART_CLK USBP0P USBP0N USBP1P USBP1N V_CPU_IO V5REF VBIAS Vcc1_8 Vcc3_3
I
I/O
Universal Serial Bus Port 1:0 Differential: These differential pairs are used to transmit Data/Address/Command signals for ports 0 and 1.
Powered by the same supply as the processor I/O voltage. This supply is used to drive the processor interface outputs. Reference for 5 V tolerance on Core well inputs. RTC well bias voltage. The DC reference voltage applied to this pin sets a current that is mirrored throughout the oscillator and buffer circuitry. See "External RTC Circuitry" on page 50. 1.8 V supply for Core well logic. 3.3 V supply for Core well I/O buffers. 3.3 V (can drop to 2.0 V minimum in the G3 state) supply for the RTC well. This power is not expected to be shut off unless the RTC battery is removed or completely drained.
VccRTC
NOTE: Implementations should not attempt to clear CMOS by using a jumper to pull VccRTC low. Clearing CMOS in an 82801E C-ICH-based platform can be done by using a jumper on RTCRST# or GPI, or using SAFEMODE strap. I VRM Power Good: This can be considered to be the CPU's VRM power good. This signal should be ANDed with the ATX power supply's PWROK signal. Grounds.
VRMPWRGD Vss
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Intel(R) 82801E C-ICH
3.2
3.2.1
Table 7.
Signals Grouped By Type
Hub Interface to Host Controller
Hub Interface Signals
Name HL[11:0] HL_STB HL_STB# HLCOMP Type I/O I/O I/O I/O Hub Interface Signals Hub Interface Strobe: One of two differential strobe signals used to transmit and receive data through the hub interface. Hub Interface Strobe Complement: Second of the two differential strobe signals. Hub Interface Compensation: Used for hub interface buffer compensation. Description
3.2.2
Table 8.
Link to LAN Connect
LAN Interface
Name LAN0_CLK LAN1_CLK LAN0_RSTSYNC LAN1_RSTSYNC LAN0_RXD[2:0] LAN1_RXD[2:0] LAN0_TXD[2:0] LAN1_TXD[2:0] Type I O Description LAN Interface Clock: This signal is driven by the LAN Connect component. The frequency range is 0.8 MHz to 50 MHz. LAN Reset/Sync: The LAN Connect component's Reset and Sync signals are multiplexed onto this pin. Received Data: The LAN Connect component uses these signals to transfer data and control information to the integrated LAN Controller. These signals have integrated weak pull-up resistors. Transmit Data: The integrated LAN Controller uses these signals to transfer data and control information to the LAN Connect component.
I
O
3.2.3
Table 9.
EEPROM Interface
EEPROM Interface
Name EE0_CS EE1_CS EE0_DIN EE1_DIN EE0_DOUT EE1_DOUT EE0_SHCLK EE1_SHCLK Type O I O O Description EEPROM Chip Select: These signals are chip-select signals to the EEPROMs. EEPROM Data In: These signals transfer data from the EEPROMs to the 82801E C-ICH. These signals have an integrated pull-up resistor. EEPROM Data Out: These signals transfer data from the 82801E C-ICH to the EEPROMs. EEPROM Shift Clock: These signals are the serial shift clock output to the EEPROMs.
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3.2.4
Firmware Hub Interface
Table 10. Firmware Hub Interface Signals
Name FWH[3:0] /LAD[3:0] FWH[4] /LFRAME# Type I/O I/O Description Firmware Hub Signals: These signals are muxed with LPC address signals. Firmware Hub Signals: This signal is muxed with the LPC LFRAME# signal.
3.2.5
PCI Interface
Table 11. PCI Interface Signals (Sheet 1 of 3)
Name Type Description PCI Address/Data: AD[31:0] is a multiplexed address and data bus. During the first clock of a transaction, AD[31:0] contain a physical address (32 bits). During subsequent clocks, AD[31:0] contain data. The 82801E C-ICH drives all 0s on AD[31:0] during the address phase of all PCI Special Cycles. Bus Command and Byte Enables: The command and byte enable signals are multiplexed on the same PCI pins. During the address phase of a transaction, C/BE[3:0]# define the bus command. During the data phase, C/BE[3:0]# define the Byte Enables. C/BE[3:0]# 0000 0001 0010 0011 0110 C/BE[3:0]# I/O 0111 1010 1011 1100 1101 1110 1111 Command Type Interrupt Acknowledge Special Cycle I/O Read I/O Write Memory Read Memory Write Configuration Read Configuration Write Memory Read Multiple DAC Mode Address to be latched (target only) Memory Read Line Memory Write and Invalidate
AD[31:0]
I/O
All command encodings not shown are reserved. The 82801E C-ICH does not decode reserved values, and therefore will not respond if a PCI master generates a cycle using one of the reserved values. As a target, the 82801E C-ICH can support DAC mode addressing for 44 bits. Device Select: The 82801E C-ICH asserts DEVSEL# to claim a PCI transaction. As an output, the 82801E C-ICH asserts DEVSEL# when a PCI master peripheral attempts an access to an internal 82801E C-ICH address or an address destined for the hub interface (main memory or AGP). As an input, DEVSEL# indicates the response to an 82801E C-ICH-initiated transaction on the PCI bus. DEVSEL# is tri-stated from the leading edge of PCIRST#. DEVSEL# remains tri-stated by the 82801E C-ICH until driven by a target device.
DEVSEL#
I/O
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Intel(R) 82801E C-ICH
Table 11. PCI Interface Signals (Sheet 2 of 3)
Name Type Description Cycle Frame: The current Initiator drives FRAME# to indicate the beginning and duration of a PCI transaction. While the initiator asserts FRAME#, data transfers continue. When the initiator negates FRAME#, the transaction is in the final data phase. FRAME# is an input to the 82801E C-ICH when the 82801E C-ICH is the target, and FRAME# is an output from the 82801E C-ICH when the 82801E C-ICH is the Initiator. FRAME# remains tri-stated by the 82801E C-ICH until driven by an Initiator. Initiator Ready: IRDY# indicates the 82801E C-ICH's ability, as an Initiator, to complete the current data phase of the transaction. It is used in conjunction with TRDY#. A data phase is completed on any clock both IRDY# and TRDY# are sampled asserted. During a write, IRDY# indicates the 82801E C-ICH has valid data present on AD[31:0]. During a read, it indicates the 82801E C-ICH is prepared to latch data. IRDY# is an input to the 82801E C-ICH when the 82801E C-ICH is the Target and an output from the 82801E C-ICH when the 82801E C-ICH is an Initiator. IRDY# remains tri-stated by the 82801E C-ICH until driven by an Initiator. Target Ready: TRDY# indicates the 82801E C-ICH's ability as a Target to complete the current data phase of the transaction. TRDY# is used in conjunction with IRDY#. A data phase is completed when both TRDY# and IRDY# are sampled asserted. During a read, TRDY# indicates that the 82801E C-ICH, as a Target, has placed valid data on AD[31:0]. During a write, TRDY# indicates the 82801E C-ICH, as a Target is prepared to latch data. TRDY# is an input to the 82801E C-ICH when the 82801E C-ICH is the Initiator and an output from the 82801E C-ICH when the 82801E C-ICH is a Target. TRDY# is tri-stated from the leading edge of PCIRST#. TRDY# remains tri-stated by the 82801E C-ICH until driven by a target. Stop: STOP# indicates that the 82801E C-ICH, as a Target, is requesting the Initiator to stop the current transaction. STOP# causes the 82801E C-ICH, as an Initiator, to stop the current transaction. STOP# is an output when the 82801E C-ICH is a target and an input when the 82801E C-ICH is an Initiator. STOP# is tri-stated from the leading edge of PCIRST#. STOP# remains tri-stated until driven by the 82801E C-ICH. Calculated/Checked Parity: PAR uses "even" parity calculated on 36 bits, AD[31:0] plus C/BE[3:0]#. "Even" parity means that the 82801E C-ICH counts the number of 1s within the 36 bits plus PAR and the sum is always even. The 82801E C-ICH always calculates PAR on 36 bits, regardless of the valid byte enables. The 82801E C-ICH generates PAR for address and data phases and only guarantees PAR to be valid one PCI clock after the corresponding address or data phase. The 82801E C-ICH drives and tri-states PAR identically to the AD[31:0] lines except that the 82801E C-ICH delays PAR by exactly one PCI clock. PAR is an output during the address phase (delayed one clock) for all 82801E C-ICH initiated transactions. PAR is an output during the data phase (delayed one clock) when the 82801E C-ICH is the Initiator of a PCI write transaction, and when it is the target of a read transaction. 82801E C-ICH checks parity when it is the target of a PCI write transaction. If a parity error is detected, the 82801E C-ICH sets the appropriate internal status bits, and has the option to generate an NMI# or SMI#. Parity Error: An external PCI device drives PERR# when it receives data that has a parity error. The 82801E C-ICH drives PERR# when it detects a parity error. The ICH can either generate an NMI# or SMI# upon detecting a parity error (either detected internally or reported via the PERR# signal). PCI Requests: The 82801E C-ICH supports up to five masters on the PCI bus. REQ[5]# is muxed with PC/PCI REQ[B]# (must choose one or the other, but not both). If not used for PCI or PC/PCI, REQ[5]#/REQ[B]# can instead be used as GPIO[1]. NOTE: REQ[0]# is programmable to have improved arbitration latency for supporting PCI-based 1394 controllers.
FRAME#
I/O
IRDY#
I/O
TRDY#
I/O
STOP#
I/O
PAR
I/O
PERR#
I/O
REQ[3:0]# /REQ[5]# /REQ[B]# /GPIO[1]
I
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Table 11. PCI Interface Signals (Sheet 3 of 3)
Name GNT[3:0]# /GNT[5]# /GNT[B]# /GPIO[17]# PCICLK Type Description PCI Grants: The 82801E C-ICH supports up to four masters on the PCI bus. O Pull-up resistors are not required on these signals. If pullups are used, they should be tied to the Vcc3_3 power rail. GNT[B]#/GNT[5]#/GPIO[17] has an internal pull-up. PCI Clock: This is a 33 MHz clock. PCICLK provides timing for all transactions on the PCI Bus. PCI Reset: 82801E C-ICH asserts PCIRST# to reset devices that reside on the PCI bus. The 82801E C-ICH asserts PCIRST# during power-up and when S/W initiates a hard reset sequence through the RC (CF9h) register. The 82801E C-ICH drives PCIRST# inactive a minimum of 1 ms after PWROK is driven active. The 82801E C-ICH drives PCIRST# active a minimum of 1 ms when initiated through the RC register. PCI Lock: PLOCK# indicates an exclusive bus operation and may require multiple transactions to complete. 82801E C-ICH asserts PLOCK# when it performs non-exclusive transactions on the PCI bus. System Error: SERR# can be pulsed active by any PCI device that detects a system error condition. Upon sampling SERR# active, the 82801E C-ICH has the ability to generate an NMI, SMI#, or interrupt. PC/PCI DMA Request [A:B]: This request serializes ISA-like DMA Requests for the purpose of running ISA-compatible DMA cycles over the PCI bus. This is used by devices such as PCI-based Super I/O or audio codecs that need to perform legacy 8237 DMA but have no ISA bus. When not used for PC/PCI requests, these signals can be used as General Purpose Inputs. Instead, REQ[B]# can be used as the fifth PCI bus request. PC/PCI DMA Acknowledges [A:B]: This grant serializes an ISA-like DACK# for the purpose of running DMA/ISA master cycles over the PCI bus. This is used by devices such as PCI-based Super/IO or audio codecs which need to perform legacy 8237 DMA but have no ISA bus. When not used for PC/PCI, these signals can be used as General Purpose Outputs. GNTB# can also be used as the fifth PCI bus master grant output. These signal have internal pull-up resistors.
I
PCIRST#
O
PLOCK#
I/O
SERR#
I
REQ[A]# /GPIO[0] REQ[B]# /REQ[5]# /GPIO[1] I
GNT[A]# /GPIO[16] GNT[B]# /GNT[5]# /GPIO[17] O
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Intel(R) 82801E C-ICH
3.2.6
IDE Interface
Table 12. IDE Interface Signals
Name PDCS1# SDCS1# PDCS3# SDCS3# PDA[2:0] SDA[2:0] PDD[15:0] SDD[15:0] Type O Description Primary and Secondary IDE Device Chip Selects for 100 Range: These signals are for the ATA command register block. This output signal is connected to the corresponding signal on the primary or secondary IDE connector. Primary and Secondary IDE Device Chip Select for 300 Range: These signals are for the ATA control register block. This output signal is connected to the corresponding signal on the primary or secondary IDE connector. Primary and Secondary IDE Device Address: These output signals are connected to the corresponding signals on the primary or secondary IDE connectors. They are used to indicate which byte in either the ATA command block or control block is being addressed. Primary and Secondary IDE Device Data: These signals directly drive the corresponding signals on the primary or secondary IDE connector. There is a weak internal pull-down resistor on PDD[7] and SDD[7]. Primary and Secondary IDE Device DMA Request: These input signals are directly driven from the DRQ signals on the primary or secondary IDE connector. It is asserted by the IDE device to request a data transfer, and used in conjunction with the PCI bus master IDE function. They are not associated with any AT-compatible DMA channel. There is a weak internal pull-down resistor on these signals. Primary and Secondary IDE Device DMA Acknowledge: These signals directly drive the DAK# signals on the primary and secondary IDE connectors. Each signal is asserted by the 82801E C-ICH to indicate to the IDE DMA slave devices that a given data transfer cycle (assertion of DIOR# or DIOW#) is a DMA data transfer cycle. This signal is used in conjunction with the PCI bus master IDE function and are not associated with any AT-compatible DMA channel. Primary and Secondary Disk I/O Read (PIO and Non-Ultra DMA): This is the command to the IDE device that it may drive data on the PDD or SDD lines. Data is latched by the 82801E C-ICH on the deassertion edge of PDIOR# or SDIOR#. The IDE device is selected either by the ATA register file chip selects (PDCS1# or SDCS1#, PDCS3# or SDCS3#) and the PDA or SDA lines, or the IDE DMA acknowledge (PDDAK# or SDDAK#). O Primary and Secondary Disk Write Strobe (Ultra DMA Writes to Disk): This is the data write strobe for writes to disk. When writing to disk, 82801E C-ICH drives valid data on rising and falling edges of PDWSTB or SDWSTB. Primary and Secondary Disk DMA Ready (Ultra DMA Reads from Disk): This is the DMA ready for reads from disk. When reading from disk, 82801E C-ICH deasserts PRDMARDY# or SRDMARDY# to pause burst data transfers. Primary and Secondary Disk I/O Write (PIO and Non-Ultra DMA): This is the command to the IDE device that it may latch data from the PDD or SDD lines. Data is latched by the IDE device on the deassertion edge of PDIOW# or SDIOW#. The IDE device is selected either by the ATA register file chip selects (PDCS1# or SDCS1#, PDCS3# or SDCS3#) and the PDA or SDA lines, or the IDE DMA acknowledge (PDDAK# or SDDAK#). Primary and Secondary Disk Stop (Ultra DMA): 82801E C-ICH asserts this signal (PDSTOP, SDSTOP) to terminate a burst. PIORDY /(PDRSTB /PWDMARDY#) SIORDY /(SDRSTB /SWDMARDY#) Primary and Secondary I/O Channel Ready (PIO): This signal keeps the strobe active (PDIOR# or SDIOR# on reads, PDIOW# or SDIOW# on writes) longer than the minimum width. It adds wait states to PIO transfers. I Primary and Secondary Disk Read Strobe (Ultra DMA Reads from Disk): When reading from disk, 82801E C-ICH latches data on rising and falling edges of this signal from the disk. Primary and Secondary Disk DMA Ready (Ultra DMA Writes to Disk): When writing to disk, this is deasserted by the disk to pause burst data transfers.
O
O
I/O
PDDREQ SDDREQ
I
PDDACK# SDDACK#
O
PDIOR# /(PDWSTB /PRDMARDY#) SDIOR# /(SDWSTB /SRDMARDY#)
PDIOW# /(PDSTOP) SDIOW# /(SDSTOP)
O
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3.2.7
LPC Interface
Table 13. LPC Interface Signals
Name LAD[3:0] /FWH[3:0] LFRAME# /FWH[4] LDRQ[1:0]# Type I/O O Description LPC Multiplexed Command, Address, Data: Internal pull-ups are provided. LPC Frame: LFRAME# indicates the start of an LPC cycle, or an abort. LPC Serial DMA/Master Request Inputs: These signals are used to request DMA or bus master access. Typically, they are connected to external Super I/O device. An internal pull-up resistor is provided on these signals.
I
3.2.8
Interrupt Interface
Table 14. Interrupt Signals
Name SERIRQ Type I/O Description Serial Interrupt Request: This pin implements the serial interrupt protocol. PCI Interrupt Requests: In Non-APIC Mode the PIRQx# signals can be routed to interrupts 3:7, 9:12, 14, or 15 as described in the Interrupt Steering section. Each PIRQx# line has a separate Route Control Register. In APIC mode, these signals are connected to the internal I/O APIC in the following fashion: PIRQ[A]# is connected to IRQ16, PIRQ[B]# to IRQ17, PIRQ[C]# to IRQ18, and PIRQ[D]# to IRQ19. This frees the ISA interrupts. PCI Interrupt Requests: In Non-APIC Mode the PIRQx# signals can be routed to interrupts 3:7, 9:12, 14 or 15 as described in the Interrupt Steering section. Each PIRQx# line has a separate Route Control Register. I/OD In APIC mode, these signals are connected to the internal I/O APIC in the following fashion: PIRQ[E]# is connected to IRQ20, PIRQ[F]# to IRQ21, PIRQ[G]# to IRQ22, and PIRQ[H]# to IRQ23. This frees the ISA interrupts. If not needed for interrupts, PIRQ[H:G] can be used as GPIO. Interrupt Request 14:15: These interrupt inputs are connected to the IDE drives. IRQ14 is used by the drives connected to the primary controller and IRQ15 is used by the drives connected to the secondary controller. APIC Clock: The APIC clock runs at 33.333 MHz. APIC Data: These bidirectional open drain signals are used to send and receive data over the APIC bus. As inputs, the data is valid on the rising edge of APICCLK. As outputs, new data is driven from the rising edge of the APICCLK.
PIRQ[A:D]#
I/OD
PIRQ[E:F]# PIRQ[G]#/GPIO[4] PIRQ[H]#/GPIO[5]
IRQ[14:15] APICCLK
I I
APICD[1:0]
I/OD
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Intel(R) 82801E C-ICH
3.2.9
USB Interface
Table 15. USB Interface Signals
Name USBP0P USBP0N USBP1P USBP1N OC[1:0]# Type Description Universal Serial Bus Port 1:0 Differential: These differential pairs are used to transmit Data/Address/Command signals for ports 0 and 1. Overcurrent Indicators: These signals set corresponding bits in the USB controllers to indicate that an overcurrent condition has occurred.
I/O
I
3.2.10
Power Signals
Table 16. Power Signals
Name PWROK Type I Description Power OK: When asserted, PWROK is an indication to the 82801E C-ICH that core power and PCICLK have been stable for at least 1 ms. PWROK can be driven asynchronously. When PWROK is negated, the 82801E C-ICH asserts PCIRST#. Resume Well Power OK: When asserted, this signal is an indication to the 82801E C-ICH that the resume well power has been stable for at least 10 ms. NOTE: The 82801E C-ICH does not use the resume well power OK signal. RSMRST# I Resume Well Reset: RSMRST# is used for resetting the resume power plane logic. NOTE: The 82801E C-ICH does not use the resume well reset signal. VRMPWRGD I VRM Power Good: VRMPWRGD should be connected to be the processor's VRM Power Good.
RSM_PWROK
I
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3.2.11
Processor Interface
Table 17. Processor Interface Signals (Sheet 1 of 2)
Name Type Description Mask A20: A20M# goes active based on setting the appropriate bit in the Port 92h register, or based on the A20GATE signal. Speed Strap: During the reset sequence, 82801E C-ICH drives A20M# high if the corresponding bit is set in the FREQ_STRP register. Processor Sleep: This signal puts the processor into a state that saves substantial power compared to Stop-Grant state. However, during that time, no snoops occur. The 82801E C-ICH can optionally assert the CPUSLP# signal when going to the S1 state. NOTE: The 82801E C-ICH does not support Sleep states. This signal must be pulled up through an 8.2 K resistor to 3.3 V. Numeric Coprocessor Error: This signal is tied to the coprocessor error signal on the processor. FERR# is only used if the 82801E C-ICH coprocessor error reporting function is enabled in the General Control Register (Device 31:Function 0, Offset D0, bit 13). If FERR# is asserted, the 82801E C-ICH generates an internal IRQ13 to its interrupt controller unit. It is also used to gate the IGNNE# signal to ensure that IGNNE# is not asserted to the processor unless FERR# is active. FERR# requires an external weak pull-up to ensure a high level when the coprocessor error function is disabled. Ignore Numeric Error: This signal is connected to the ignore error pin on the processor. IGNNE# is only used if the 82801E C-ICH coprocessor error reporting function is enabled in the General Control Register (Device 31:Function 0, Offset D0, bit 13). If FERR# is active, indicating a coprocessor error, a write to the Coprocessor Error Register (F0h) causes the IGNNE# to be asserted. IGNNE# remains asserted until FERR# is negated. If FERR# is not asserted when the Coprocessor Error Register is written, the IGNNE# signal is not asserted. Speed Strap: During the reset sequence, 82801E C-ICH drives IGNNE# high if the corresponding bit is set in the FREQ_STRP register. INIT# O Initialization: INIT# is asserted by the 82801E C-ICH for 16 PCI clocks to reset the processor. 82801E C-ICH can be configured to support processor BIST. In that case, INIT# will be active when PCIRST# is active. Processor Interrupt: INTR is asserted by the 82801E C-ICH to signal the processor that an interrupt request is pending and needs to be serviced. It is an asynchronous output and normally driven low. Speed Strap: During the reset sequence, 82801E C-ICH drives INTR high if the corresponding bit is set in the FREQ_STRP register. Non-Maskable Interrupt: NMI is used to force a non-maskable interrupt to the processor. The 82801E C-ICH can generate an NMI when either SERR# or IOCHK# is asserted. The processor detects an NMI when it detects a rising edge on NMI. NMI is reset by setting the corresponding NMI source enable/disable bit in the NMI Status and Control Register. Speed Strap: During the reset sequence, 82801E C-ICH drives NMI high if the corresponding bit is set in the FREQ_STRP register. SMI# O System Management Interrupt: SMI# is an active low output synchronous to PCICLK. It is asserted by the 82801E C-ICH in response to one of many enabled hardware or software events. Stop Clock Request: STPCLK# is an active low output synchronous to PCICLK. It is asserted by the 82801E C-ICH in response to one of many hardware or software events. When the processor samples STPCLK# asserted, it responds by stopping its internal clock.
A20M#
O
CPUSLP#
O
FERR#
I
IGNNE#
O
INTR
O
NMI
O
STPCLK#
O
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Intel(R) 82801E C-ICH
Table 17. Processor Interface Signals (Sheet 2 of 2)
Name Type Description Keyboard Controller Reset Processor: The keyboard controller can generate INIT# to the processor. This saves the external OR gate with the 82801E C-ICH's other sources of INIT#. When the 82801E C-ICH detects the assertion of this signal, INIT# is generated for 16 PCI clocks. A20 Gate: This signal is from the keyboard controller. It acts as an alternative method to force the A20M# signal active. A20GATE saves the external OR gate needed with various other PCIsets. Processor Power Good: This signal should be connected to the processor's PWRGOOD input. This is an open-drain output signal (external pull-up resistor required) that represents a logical AND of the 82801E C-ICH's PWROK and VRMPWRGD signals.
RCIN#
I
A20GATE
I
CPUPWRGD
OD
3.2.12
SMBus Interface
Table 18. SMBus Interface Signals
Name SMBDATA SMBCLK SMBALERT# /GPIO[11] Type I/OD I/OD I Description SMBus Data: External pull-up is required. SMBus Clock: External pull-up is required. SMBus Alert: This signal is used to wake the system or generate an SMI#. If not used for SMBALERT#, it can be used as a GPI.
3.2.13
System Management Interface
Table 19. System Management Interface Signals
Name INTRUDER# Type I Description Intruder Detect: This signal can be set to disable system if box detected open. This signal's status is readable, so it can be used like a GPI if the Intruder Detection is not needed. System Management Link: These signals are an SMBus link to an optional external system management ASIC or LAN controller. External pull-ups are required. NOTE: SMLINK[0] corresponds to an SMBus Clock signal and SMLINK[1] corresponds to an SMBus Data signal.
SMLINK[1:0]
I/OD
3.2.14
Real Time Clock Interface
Table 20. Real Time Clock Interface
Name RTCX1 RTCX2 Type Special Special Description Crystal Input 1: This signal is connected to the 32.768 KHz crystal. If no external crystal is used, then RTCX1 can be driven with the desired clock rate. Crystal Input 2: This signal is connected to the 32.768 KHz crystal. If no external crystal is used, then RTCX2 should be left floating.
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3.2.15
Other Clocks
Table 21. Other Clocks
Name CLK14 CLK48 CLK66 (HLCLK) Type I I I Description Oscillator Clock: CLK14 is used for 8254 timers and runs at 14.31818 MHz. 48 MHz Clock: CLK48 is used to for the USB controller and runs at 48 MHz. 66 MHz Clock (HLCLK): CLK66 is used for the hub interface and runs at 66 MHz.
3.2.16
Universal Asynchronous Receive and Transmit (UART 0,1)
Table 22. Universal Asynchronous Receive And Transmit (UART 0, 1) (Sheet 1 of 2)
Signal Name UART_CLK Type I Description Input clock to the SIU. This clock is passed to the baud clock generation logic of each UART in the SIU. Clear to Send: Active low, this pin indicates that data can be exchanged between CICH and external interface. These pins have no effect on the transmitter. SIU0_CTS# SIU1_CTS# I NOTE: These pins could be used as Modem Status Inputs whose condition can be tested by the processor by reading bit 4 (CTS) of the Modem Status register (MSR). Bit 4 is the complement of the CTS# signal. Bit 0 (DCTS) of the MSR indicates whether the CTS# input has changed state since the previous reading of the MSR. When the CTS bit of the MSR changes state an interrupt is generated if the Modem Status Interrupt is enabled. Data Carrier Detect for UART0 and UART1: Active low, this pin indicates that data carrier has been detected by the external agent. SIU0_DCD# SIU1_DCD# I NOTE: These pins are Modem Status Inputs whose condition can be tested by the processor by reading bit 7 (DCD) of the Modem Status register (MSR). Bit 7 is the complement of the DCD# signal. Bit 3 (DDCD) of the MSR indicates whether the DCD# input has changed state since the previous reading of the MSR. When the DCD bit of the MSR changes state an interrupt is generated if the Modem Status Interrupt is enabled. Data Set Ready for UART0 and UART1: Active low, this pin indicates that the external agent is ready to communicate with 82801E C-ICH UARTs. These pins have no effect on the transmitter. SIU0_DSR# SIU1_DSR# I NOTE: These pins could be used as Modem Status Input whose condition can be tested by the processor by reading bit 5 (DSR) of the Modem Status register. Bit 5 is the complement of the DSR# signal. Bit 1 (DDSR) of the Modem status register (MSR) indicates whether the DSR# input has changed state since the previous reading of the MSR. When the DSR bit of the MSR changes state an interrupt is generated if the Modem Status Interrupt is enabled. Data Terminal Ready for UART0 and UART1: When low these pins informs the modem or data set that 82801E C-ICH UART0 and UART1 are ready to establish a communication link. The DTR#x(x=0,1) output signals can be set to an active low by programming the DTRx (x-0,1) (bit0) of the Modem control register to a logic `1'. A Reset operation sets this signal to its inactive state (logic `1'). LOOP mode operation holds this signal in its inactive state.
SIU0_DTR# SIU1_DTR#
O
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Table 22. Universal Asynchronous Receive And Transmit (UART 0, 1) (Sheet 2 of 2)
Signal Name Type Description Ring Indicator for UART0 and UART1: Active low, this pin indicates that a telephone ringing signal has been received by the external agent. SIU0_RI# SIU1_RI# I NOTE: These pins are Modem Status Input whose condition can be tested by the processor by reading bit 6 (RI) of the Modem Status register (MSR). Bit 6 is the complement of the RI# signal. Bit 2 (TERI) of the MSR indicates whether the DCD# input has changed state since the previous reading of the MSR. When the RI bit of the MSR changes state an interrupt is generated if the Modem Status Interrupt is enabled. Request to Send for UART0 and UART1: When low these pins informs the modem or data set that 82801E C-ICH UART0 and UART1 are ready to establish a communication link. The RTS#x(x=0,1) output signals can be set to an active low by programming the RTSx (x-0,1) (bit1) of the Modem control register to a logic `1'. A Reset operation sets this signal to its inactive state (logic `1'). LOOP mode operation holds this signal in its inactive state. Serial Inputs for UART0 and UART1: Serial data input from device pin to the receive port. Serial Output for UART0 and UART1: Serial data output to the communication peripheral/modem or data set. Upon reset, the TXD pins will be set to MARKING condition (logic `1' state).
SIU0_RTS# SIU1_RTS#
O
SIU0_RXD SIU1_RXD SIU0_TXD SIU1_TXD
I
O
3.2.17
SIU LPC Interface
Table 23. SIU Interface
Signal Name SIU_LAD[3:0] SIU_LCLK SIU_LDRQ# SIU_LFRAME# SIU_RESET# SIU_SERIRQ Type I/O I O I I I/O Description SIU LPC Multiplexed Command, Address, Data: Internal pull-ups are provided. SIU LPC clock input to SIU: 33 MHz LPC clock. SIU LPC Serial DMA/Master Request Output: Used by SIU devices to indicate a DMA request. NOTE: These signals have weak internal pull-up resistors to avoid external glue. SIU LPC Frame: Indicates the start of an LPC cycle, or an abort. SIU RESET: This signal should be tied to PCI RESET. SIU Serial IRQ input: This pin receives the serial interrupt protocol from external devices. Pull up if unused.
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3.2.18
Miscellaneous Signals
Table 24. Miscellaneous Signals
Name HL[11] Type I Description No pull-up required. Use a no-stuff or a test point for NAND tree testing. RTC Reset: When asserted, this signal resets register bits in the RTC well and sets the RTC_PWR_STS bit (bit 2 in GEN_PMCON3 register). This signal is also used to enter the test modes documented in "Test Signals" on page 49. RTCRST# I NOTE: Clearing CMOS in an 82801E C-ICH-based platform can be done by using a jumper on RTCRST# or GPI, or using SAFEMODE strap. Implementations should not attempt to clear CMOS by using a jumper to pull VccRTC low. Speaker: The SPKR signal is the output of counter 2 and is internally ANDed with Port 61h bit 1 to provide Speaker Data Enable. This signal drives an external speaker driver device, which in turn drives the system speaker. Upon PCIRST#, its output state is 1. NOTE: SPKR is sampled at the rising edge of PWROK as a functional strap. See "Functional Straps" on page 49for more details. TP0 THRM# I I Test Point 0: This signal must have an external pull-up to Vcc3_3. Thermal Alarm: THRM# is an active low signal generated by external hardware to start the hardware clock throttling mode. This signal can also generate an SMI# or an SCI. Ring Indicate: From the modem interface. This signal can be enabled as a wake event; this is preserved across power failures. This signal must have an external pull up to Vcc3_3. Suspend Clock: This signal is an output of the RTC generator circuit and is used by other chips for the refresh clock. Test Point 1: Route to a test point with option to jumper to Vcc1_8. Used for NAND tree testing. Otherwise jumper to Vcc1_8. Test Point 2: Route to a test point with option to jumper to V SS. Used for NAND tree testing. Otherwise jumper to VSS. Test Point 3: Route to a test point with option to jumper to V SS. Used for NAND tree testing. Otherwise jumper to VSS.
SPKR
O
RI# RESERVED1 RESERVED2 SUSCLK TP1 TP2 TP3
I -- O I I I
3.2.19
General Purpose I/O
Table 25. General Purpose I/O Signals (Sheet 1 of 2)
Name GPIO[31:29] GPIO[28:27] GPIO[26] GPIO[25] GPIO[24] GPIO[23] GPIO[22] Type O I/O I/O I/O I/O O OD Not implemented. Can be input or output. Main power well. Unmuxed. Not implemented. Can be input or output. Main power well. Not Muxed. Can be input or output. Main power well. Fixed as Output only. Main power well. Fixed as Output only. Main power well. Open-drain output. Description
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Table 25. General Purpose I/O Signals (Sheet 2 of 2)
Name GPIO[21] GPIO[20:18] GPIO[17:16] GPIO[15:14] GPIO[13:12] GPIO[11] GPIO[10:9] GPIO[8] GPIO[7] GPIO[6] GPIO[5:4] GPIO[3:2] GPIO[1:0] I Type O O O I I I I I I I I Description Fixed as Output only. Main power well. Fixed as Output only. Main power well. Fixed as Output only. Main Power Well. Can instead be used for PC/PCI GNT[A:B]#. GPIO[17] can also alternatively be used for PCI GNT[5]#. Integrated pull-up resistor. Not implemented. Fixed as Input only. Main Power Well. Not muxed. Fixed as Input only. Main Power Well. Can instead be used for SMBALERT#. Not implemented. Fixed as Input only. Main Power Well. Not muxed. Fixed as Input only. Main power well. Not muxed. Fixed as Input only. Main power well. Fixed as Input only. Main power well. Can be used instead as PIRQ[G:H]#. Reserved. Fixed as Input only. Main Power Well. Can instead be used for PC/PCI REQ[A:B]#. GPIO[1] can also alternatively be used for PCI REQ[5]#.
3.2.20
Power and Ground
Table 26. Power and Ground Signals
Name HUBREF V5REF VBIAS Vcc1_8 Vcc3_3 0.9 V reference for the hub interface. Reference for 5 V tolerance on Core well inputs. RTC well bias voltage. The DC reference voltage applied to this pin sets a current that is mirrored throughout the oscillator and buffer circuitry. See "External RTC Circuitry" on page 50. 1.8 V supply for Core well logic. 3.3 V supply for Core well I/O buffers. 3.3 V (can drop to 2.0 V min. in G3 state) supply for the RTC well. This power is not expected to be shut off unless the RTC battery is removed or completely drained. VccRTC NOTE: Implementations should not attempt to clear CMOS by using a jumper to pull VccRTC low. Clearing CMOS in an 82801E C-ICH-based platform can be done by using a jumper on RTCRST# or GPI, or using SAFEMODE strap. Powered by the same supply as the processor I/O voltage. This supply is used to drive the processor interface outputs. Ground. Description
V_CPU_IO Vss
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3.3
3.3.1
Pin Straps
Functional Straps
The following signals are used for static configuration. They are sampled at the rising edge of PWROK to select configurations and then revert later to their normal usage. To invoke the associated mode, the signal should be driven at least four PCI clocks prior to the time it is sampled.
Table 27. Functional Strap Definitions
Signal Usage When Sampled Comment System designers should include a placeholder for a pull-down resistor on EEn_DOUT but do not populate the resistor. The signal has a weak internal pull-up. If the signal is sampled low, the system is strapped to the "Top-Swap" mode (82801E C-ICH will invert A16 for all cycles targeting FWH BIOS space). The status of this strap is readable via the Top-Swap bit (bit 13, D31: F0, Offset D4h). Note that software will not be able to clear the Top-Swap bit until the system is rebooted without GNT[A]# being pulled down. If this signal is sampled high (via an external pull-up to VCC1_8), the normal hub interface buffer mode will be selected. If this signal is sampled low (via an external pull-down), the enhanced hub interface buffer mode will be selected. See the specific platform design guide for resistor values and routing guidelines for each hub interface mode. The signal has a weak internal pull-up. If the signal is sampled low, the system is strapped to the "No Reboot" mode (82801E C-ICH will disable the TCO Timer system reboot feature). The status of this strap is readable via the NO_REBOOT bit (bit 1, D31: F0, Offset D4h).
EE0_DOUT, Reserved EE1_DOUT
GNT[A]#
Top-Swap Override
Rising Edge of PWROK
HLCOMP
Enhanced Hub Interface Mode
During PCIRST# assertion
SPKR
Rising No Reboot Edge of PWROK
3.3.2
3.3.2.1
Test Signals
Test Mode Selection
When PWROK is active (high), driving RTCRST# low for a number of PCI clocks (33 MHz) will activate a particular test mode as specified in Table 28. Note: RTCRST# may be driven low any time after PCIRST is inactive. Refer to "Testability" on page 77 for a detailed description of the 82801E C-ICH test modes.
Table 28. Test Mode Selection
Number of PCI Clocks RTCRST# driven low after PWROK active <4 4 5 6 7 Test Mode No Test Mode Selected XOR Chain 1 XOR Chain 2 XOR Chain 3 XOR Chain 4
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Table 28. Test Mode Selection
Number of PCI Clocks RTCRST# driven low after PWROK active 8 9-24 >24 Test Mode All "Z" Reserved. DO NOT ATTEMPT No Test Mode Selected
3.3.2.2
Test Straps
* The 82801E C-ICH's TP[0] (Test Point) signal must be pulled to Vcc3_3 with an external
pull-up resistor.
* The 82801E C-ICH's TP[1] must be routed to a test point with an option to jumper to Vcc1_8.
This test point is used for NAND tree testing. Otherwise jumper to Vcc1_8.
* The 82801E C-ICH's TP[2] must be routed to a test point with an option to jumper to V SS.
This test point is used for NAND tree testing. Otherwise jumper to V SS.
* The 82801E C-ICH's TP[3] must be routed to a test point with an option to jumper to V SS.
This test point is used for NAND tree testing. Otherwise jumper to V SS.
3.3.3
External RTC Circuitry
To reduce RTC well power consumption, the 82801E C-ICH implements an internal oscillator circuit that is sensitive to step voltage changes in VccRTC and VBIAS. Figure 7 shows a schematic diagram of the circuitry required to condition these voltages to ensure correct operation of the 82801E C-ICH RTC.
Figure 7. Required External RTC Circuit
3.3V VCCSUS 1 k 1 F RTCX2 Vbatt 1 k 32768 Hz Xtal R1 10 M RTCX1 C1 0.047 uF C3 12.5 pF R2 10 M VBIAS C2 12.5 pF VSSRTC Note: Capacitor C2 and C3 values are crystal-dependent. VCCRTC
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3.3.4
V5REF/Vcc3_3 Sequencing Requirements
V5REF is the reference voltage for 5 V tolerance on inputs to the 82801E C-ICH. V5REF must power up before or simultaneous to Vcc3_3, and must power down after or simultaneous to Vcc3_3. Refer to Figure 8 for an example circuit schematic that may be used to ensure proper V5REF sequencing.
Figure 8. Example V5REF Sequencing Circuit
VCC Supply (3.3V) 1k
Schottky Diode
5V Supply
1 uF
To System
5VREF
To System
3.4
3.4.1
Power Planes and Pin States
Power Planes
Table 29. 82801E C-ICH Power Planes
Plane Main I/O (3.3 V) Main Logic (1.8 V) Processor Interface (1.3 ~ 2.5 V) RTC Description Vcc3_3: Powered by the main power supply. Vcc1_8: Powered by the main power supply. V_CPU_IO: Powered by the main power supply via processor voltage regulator. VccRTC: When other power is available (from the main supply), external diode coupling will provide power to reduce the drain on the RTC battery. Assumed to operate from 3.3 V down to 2.0 V.
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3.4.2
Integrated Pull-Ups and Pull-Downs
Table 30. Integrated Pull-Up and Pull-Down Resistors
Signal EE0_DIN, EE1_DIN EE0_DOUT, EE1_DOUT GNT[A:B]#/GNT[5]#/GPIO[17:16] LAD[3:0]#/FWH[3:0]# LDRQ[1:0] SPKR LAN0_RXD[2:0], LAN1_RXD[2:0] PDD[7]/SDD[7] PDDREQ/SDDREQ Resistor Type pull-up pull-up pull-up pull-up pull-up pull-up pull-up pull-down pull-down Nominal Value 24 K 24 K 24 K 24 K 24 K 24 K 9 K 5.9 K 5.9 K Notes 1 1 1 1 1 1, 4 2 3 3
NOTES: 1. Simulation data shows that these resistor values can range from 18 K to 42 K. 2. Simulation data shows that these resistor values can range from 6 K to 14 K. 3. Simulation data shows that these resistor values can range from 4.3 K to 20 K. 4. The pull-up or pull-down on this signal is only enabled at boot/reset for strapping function.
3.4.3
IDE Integrated Series Termination Resistors
Table 31 shows the 82801E C-ICH IDE signals that have integrated series termination resistors.
Table 31. IDE Series Termination Resistors
Signal PDD[15:0], SDD[15:0], PDIOW#, SDIOW#, PDIOR#, PDIOW#, PDREQ, SDREQ, PDDACK#, SDDACK#, PIORDY, SIORDY, PDA[2:0], SDA[2:0], PDCS1#, SDCS1#, PDCS3#, SDCS3#, IRQ14, IRQ15 Integrated Series Termination Resistor Value
approximately 33 (See Note)
NOTE: Simulation data indicates that the integrated series termination resistors are a nominal 33 but can range from 31 to 43 .
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3.4.4
Output and I/O Signals Planes and States
Table 32 shows the power plane associated with the output and I/O signals, as well as the state at various times. Within the table, the following terms are used:
"High-Z" "High" "Low" "Defined" "Undefined" "Running" "Off" Tri-state. 82801E C-ICH not driving the signal high or low. The 82801E C-ICH is driving the signal to a logic `1'. The 82801E C-ICH is driving the signal to a logic `0'. The signal is driven to a level that is defined by the function (will be high or low). The 82801E C-ICH is driving the signal, but the value is indeterminate. The clock is toggling or signal is transitioning because function not stopping. The power plane is off; the 82801E C-ICH is not driving.
Table 32. Power Plane and States for Output and I/O Signals (Sheet 1 of 3)
Signal Name Power Plane Reset Signal PCI Bus AD[31:0] C/BE#[3:0] DEVSEL# FRAME# GNT[3:0]#, GNT[5]# GNT[A:B]# IRDY#, TRDY# PAR PCIRST# PERR# PLOCK# STOP# Main I/O Main I/O Main I/O Main I/O Main I/O Main I/O Main I/O Main I/O Main I/O Main I/O Main I/O Main I/O PCIRST# PCIRST# PCIRST# PCIRST# PCIRST# PCIRST# PCIRST# PCIRST# RSMRST# PCIRST# PCIRST# PCIRST# LPC Interface LAD[3:0] LFRAME# Main I/O Main I/O PCIRST# PCIRST# High High High High High-Z High-Z High-Z High-Z High High-Z High-Z High-Z Low High-Z High-Z High-Z Undefined Undefined High-Z High-Z High High High-Z Undefined High High-Z High-Z High-Z During Reset Immediately after Reset
LAN Connect and EEPROM Interface EE0_CS, EE1_CS LAN I/O RSM_PWROK Low Running
NOTES: 1. The 82801E C-ICH sets these signals at reset for processor frequency strap. 2. I GPIO[18] will toggle at a frequency of approximately 1 Hz when the 82801E C-ICH comes out of reset 3. CPUPWRGD is an open-drain output that represents a logical AND of the VRMPWRGD and PWROK signals and, thus, are driven low by 82801E C-ICH when either VRMPWRGD or PWROK are inactive. During boot, or during a hard reset with power cycling, CPUPWRGD will be expected to transition from low to High-Z. 4. GPIO[24:25, 27:28]: These signals remain tri-stated for up to 110 ms after RSMRST# deassertion. At this point, they will be driven to their default (High) state.
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Table 32. Power Plane and States for Output and I/O Signals (Sheet 2 of 3)
Signal Name EE0_DOUT, EE1_DOUT EE0_SHCLK, EE1_SHCLK LAN0_RSTSYNC, LAN1_RSTSYNC LAN0_TXD[2:0], LAN1_TXD[2:0] Power Plane LAN I/O LAN I/O LAN I/O LAN I/O Reset Signal RSM_PWROK RSM_PWROK RSM_PWROK RSM_PWROK IDE Interface PDA[2:0], SDA[2:0] PDCS1#, PDCS3# PDD[15:0], SDD[15:0] PDDACK#, SDDACK# PDIOR#, PDIOW# SDCS1#, SDCS3# SDIOR#, SDIOW# Main I/O Main I/O Main I/O Main I/O Main I/O Main I/O Main I/O PCIRST# PCIRST# PCIRST# PCIRST# PCIRST# PCIRST# PCIRST# Interrupts PIRQ[A:H]# SERIRQ APICD[1:0] Main I/O Main I/O Main I/O PCIRST# PCIRST# PCIRST# USB Interface USBP0P, USBP0N, USBP1P, USBP1N Main I/O RSMRST# Processor Interface A20M# CPUPWRGD CPUSLP# IGNNE# INIT# INTR NMI SMI# CPU I/O Main I/O CPU I/O CPU I/O CPU I/O CPU I/O CPU I/O CPU I/O PCIRST# PCIRST# PCIRST# PCIRST# PCIRST# PCIRST# PCIRST# PCIRST# See Note 1 See Note 3 High See Note 1 High See Note 1 See Note 1 High High High-Z High High High Low Low High High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z Low High High-Z High High High High Undefined High High-Z High High High High During Reset High Low High Low Immediately after Reset Running Running Defined Defined
NOTES: 1. The 82801E C-ICH sets these signals at reset for processor frequency strap. 2. I GPIO[18] will toggle at a frequency of approximately 1 Hz when the 82801E C-ICH comes out of reset 3. CPUPWRGD is an open-drain output that represents a logical AND of the VRMPWRGD and PWROK signals and, thus, are driven low by 82801E C-ICH when either VRMPWRGD or PWROK are inactive. During boot, or during a hard reset with power cycling, CPUPWRGD will be expected to transition from low to High-Z. 4. GPIO[24:25, 27:28]: These signals remain tri-stated for up to 110 ms after RSMRST# deassertion. At this point, they will be driven to their default (High) state.
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Table 32. Power Plane and States for Output and I/O Signals (Sheet 3 of 3)
Signal Name STPCLK# Power Plane CPU I/O Reset Signal PCIRST# SMBus Interface SMBCLK, SMBDATA Main I/O RSMRST# High-Z High-Z During Reset High Immediately after Reset High
System Management Interface SMLINK[1:0] Main I/O RSMRST# High-Z High-Z
Miscellaneous Signals SPKR SUSCLK Main I/O Main I/O PCIRST# RSMRST# High-Z with internal pull-up Running Low
Unmuxed GPIO Signals GPIO[18] GPIO[19:20] GPIO[21] GPIO[22] GPIO[23] GPIO[24] GPIO[25] GPIO[27:28] Main I/O Main I/O Main I/O Main I/O Main I/O Main I/O Main I/O Main I/O PCIRST# PCIRST# PCIRST# PCIRST# PCIRST# RSMRST# RSMRST# RSMRST# High High High High-Z Low High-Z High-Z HIgh-Z See Note 2 High High High-Z Low High High High
NOTES: 1. The 82801E C-ICH sets these signals at reset for processor frequency strap. 2. I GPIO[18] will toggle at a frequency of approximately 1 Hz when the 82801E C-ICH comes out of reset 3. CPUPWRGD is an open-drain output that represents a logical AND of the VRMPWRGD and PWROK signals and, thus, are driven low by 82801E C-ICH when either VRMPWRGD or PWROK are inactive. During boot, or during a hard reset with power cycling, CPUPWRGD will be expected to transition from low to High-Z. 4. GPIO[24:25, 27:28]: These signals remain tri-stated for up to 110 ms after RSMRST# deassertion. At this point, they will be driven to their default (High) state.
3.4.5
Power Planes for Input Signals
Table 33 shows the power plane associated with each input signal, as well as what device drives the signal at various times. Valid states include:
* * * * *
High Low Static: Will be high or low, but will not change Driven: Will be high or low, and is allowed to change Running: For input clocks
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Table 33. Power Plane for Input Signals
Signal Name A20GATE APICCLK CLK14 CLK48 CLK66 EE0_DIN, EE1_DIN FERR# INTRUDER# IRQ[15:14] LAN0_CLK, LAN1_CLK RSM_PWROK LAN0_RXD[2:0], LAN1_RXD[2:0] LDRQ[0]# LDRQ[1]# OC[1:0]# PCICLK PDDREQ PIORDY PWROK RCIN# REQ[3:0]#, REQ[5]# REQ[B:A]# RI# RSMRST# RTCRST# SDDREQ SERR# SIORDY SMBALERT# THRM# VRMPWRGD Power Well Main I/O Main I/O Main I/O Main I/O Main Logic LAN I/O Main I/O RTC Main I/O LAN I/O Main I/O LAN I/O Main I/O Main I/O Main I/O Main I/O Main I/O Main I/O Main I/O Main I/O Main I/O Main I/O Main I/O RTC RTC Main I/O Main I/O Main I/O Main I/O Main I/O Main I/O Driver During Reset External Microcontroller Clock Generator Clock Generator Clock Generator Clock Generator EEPROM component CPU External Switch IDE LAN Connect component External RC Circuit LAN Connect component LPC Devices LPC Devices External Pull-Ups Clock Generator IDE Device IDE Device System Power Supply External Microcontroller PCI Master PC/PCI Devices Serial Port Buffer External RC circuit External RC circuit IDE Drive PCI Bus Peripherals IDE Drive External pull-up Thermal Sensor CPU Voltage Regulator
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4.0
Note:
Electrical Characteristics
This document contains information on products in the sampling and initial production phases of development. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.
4.1
Absolute Maximum Ratings
Table 34. Absolute Maximum Ratings
Case Temperature under Bias Storage Temperature Voltage on Any 3.3 V Pin with Respect to Ground Voltage on Any 5 V Tolerant Pin with Respect to Ground (VREF=5 V) 1.8 V Supply Voltage with Respect to Vss 3.3 V Supply Voltage with Respect to Vss 5.0 V Supply Voltage (Vref) with Respect to Vss Maximum Power Dissipation 0 C to +109 C -55 C to +150 C -0.5 to Vcc + 0.3 V -0.5 to VREF + 0.3 V -0.5 to +2.7V -0.5 to +4.6 V -0.5 to +5.5 V 2.0 W
Note: Warning:
A non-condensing environment is required to maintain RTC accuracy. Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. See Section 4.2 for the Functional Operating Range of the 82801E C-ICH.
4.2
Functional Operating Range
All of the AC and DC Characteristics specified in this document assume that the 82801E C-ICH component is operating within the Functional Operating Range given in this section. Operation outside of the Functional Operating Range is not recommended, and extended exposure outside of the Functional Operating Range may affect component reliability.
Table 35. Functional Operating Range
Case Temperature under Bias 1.8 V Supply Voltage (VCC1_8) with respect to Vss 3.3 V Supply Voltage (VCC3_3) with respect to Vss 5 V Supply Voltage (V5REF) with respect to Vss 0 C to +109 C 1.7 V to 1.9 V 3.102 V to 3.498 V 4.75 V to 5.25 V
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4.3
DC Characteristics
Table 36. 82801E C-ICH Power Consumption Measurements
Power Plane 1.8 V Core 3.3 V I/O 1.8 V LAN 3.3 V LAN (LAN+LAN Connect Component) Maximum Sustain Supply Current ICC (max) 300 mA 410 mA 30 mA 186 mA
Table 37. DC Characteristic Input Signal Association
Symbol Associated Signals PCI Signals: AD[31:0], C/BE[3:0]#, DEVSEL#, FRAME#, IRDY#, TRDY#, STOP#, PAR, PERR#, PLOCK#, SERR#, REQ[4:0]# PC/PCI Signals: REQ[A]#/GPIO[0], REQB[#]/REQ[5]#/GPIO[1] IDE Signals: PDD[15:0], SDD[15:0], PDDREQ, PIORDY, SDDREQ, SIORDY VIH1/VIL1 (5 V Tolerant) Interrupt Signals: IRQ[15:14], SERIRQ, PIRQ[D:A]#, PIRQ[H]#, PIRQ[F:G]#/GPIO[4:3], PIRQ[E]# Legacy Signals: RCIN#, A20GATE USB Signals: OC[1:0]# GPIO Signals: GPIO[7:6, 4:3, 1:0] VIH2/VIL2 Clock Signals: CLK66, CLK48, CLK14, LAN_CLK, PCICLK LPC/FWH Signals: LDRQ[1:0]#, LAD[3:0]/FWH[3:0]. System Management Signals: SMBALERT#/GPIO[11] VIH3/VIL3 EEPROM Signals: EE_DIN Power Management Signals: PME#, PWRBTN#, RI#, RSM_PWROK, RTCRST#, THRM#, VRMPWRGD GPIO Signals: GPIO[25:24, 13:12, 8] VIH4/VIL4 Clock Signals: APICCLK SMBus Signals: SMBCLK, SMBDATA System Management Signals: INTRUDER#, SMLINK[1:0] VIH5/VIL5 Power Management Signals: RSMRST#, PWROK, GPIO Signals: GPIO[28:27] VIL6/VIH6 V IL7/VIH7 V IL8/VIH8 VDI/VCM /VSE V IL9/VIH9 LAN Signals: LAN0_RXD[2:0], LAN1_RXD[2:0] Processor Signals: FERR#, APICD[1:0] Hub Interface Signals: HL[11:0], HL_STB#, HL_STB USB Signals: USBP0P, USBP0N, USBP1P, USBP1N RTCX1
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Table 38. DC Input Characteristics
Symbol VIL1 VIH1 VIL2 VIH2 VIL3 VIH3 VIL4 VIH4 VIL5 VIH5 VIL6 VIH6 VIL7 VIH7 VIL8 VIH8 VDI VCM VSE VIL9 VIH9 Parameter Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Min. -0.5 2.0 -0.5 2.0 -0.5 0.5 Vcc3_3 -0.5 1.7 -0.5 2.1 -0.5 0.6 Vcc3_3 -0.5 1.2 -0.5 HUBREF - 0.20 HUBREF + 0.15 Input High Voltage HUBREF + 0.20 Differential Input Sensitivity Differential Common Mode Range Single-Ended Receiver Threshold Input Low Voltage Input High Voltage 0.2 0.8 0.8 -0.5 0.40 2.5 2.0 0.10 2.0 V V V V V Vcc1_8 + 0.5 V Enhanced Mode Note 1 Note 2 Max 0.8 V5REF + 0.5 0.8 Vcc3_3 + 0.5 0.3Vcc3_3 Vcc3_3 + 0.5 0.7 2.625 0.6 Vcc3_3 + 0.5 0.3Vcc3_3 Vcc3_3 + 0.5 0.6 Vcc3_3 + 0.5 HUBREF - 0.15 V Enhanced Mode Normal Mode Unit V V V V V V V V V V V V V V Normal Mode Notes
NOTES: 1. VDI = | USBPx[P] - USBPx[N] | 2. Includes VDI range.
Table 39. DC Characteristic Output Signal Association (Sheet 1 of 2)
Symbol V OH1/VOL1 VOH2/VOL2 Associated Signals IDE Signals: PDD[15:0], SDD[15:0], PDIOW#/PDSTOP, SDIOW#/SDSTOP, PDIOR#/PDWSTB/PRDMARDY#, SDIOR#/STWSTB/SRDMARDY#, PDDACK#, SDDACK#, PDA[2:0], SDA[2:0], PDCS[3,1]#, SDCS[3,1]# Processor Signals: A20M#, CPUPWRGD, CPUSLP#, IGNNE#, INIT#, INTR, NMI, SMI#, STPCLK# PCI Signals: AD[31:0], C/BE[3:0]#, PCIRST#, GNT[5, 3:0]#, PAR, DEVSEL#, PERR#, PLOCK#, STOP#, TRDY#, IRDY#, FRAME#, SERR# Interrupt Signals: SERIRQ, PIRQ[A:F]#, PIRQ[G:H]#/GPIO[5:4]
VOH3/VOL3
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Table 39. DC Characteristic Output Signal Association (Sheet 2 of 2)
Symbol Associated Signals PCI Signals: GNT[5]#/GNT[B]#/GPIO[17], GNT[A]#/GPIO[16] LPC/FWH Signals: LAD[3:0]/FWH[3:0], LFRAME#/FWH[4] VOH4/VOL4 LAN Signals: LAN0_RSTSYNC, LAN1_RSTSYNC, LAN0_TXD[2:0], LAN1_TXD[2:0] GPIO Signals: GPIO[21] SMBus Signals: SMBCLK, SMBDATA VOL5/VOH5 System Management Signals: SMLINK[1:0] Interrupt Signals: APICD[1:0] EEPROM Signals: EE0_CS, EE1_CS, EE0_DOUT, EE1_DOUT, EE0_SHCLK, EE1_SHCLK VOL6/VOH6 Other Signals: SPKR GPIO Signals: GPIO[28:27, 25:22, 20:18] VOL7/VOH7 VOL8/VOH8 USB Signals: USBP0P, USBP0N, USBP1P, USBP1N Hub Signals: HL[11:0], HL_STB#, HL_STB
Table 40. DC Output Characteristics
Symbol VOL1 V OH1 VOL2 VOH2 VOL3 VOH3 VOL4 VOH4 VOL5 VOH5 VOL6 VOH6 VOL7 V OH7 VOL8 VOH8 Parameter Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage 0.9 x (Vcc1_8) 1.6 Vcc - 0.5 0.1 x (Vcc1_8) 0.8 Output High Voltage Vcc3_3 - 0.5 0.4 N/A 0.4 0.9 Vcc 0.4 2.4 0.1 Vcc V_CPU_IO - 0.13V 0.55 2.4 0.4 Min. Max 0.5 Unit V V V V V V V V V V V V V V V V V V 4.0 mA -2.0 mA 5 mA -2 mA 1 mA 20 mA -1 mA -1.5 mA Normal Mode Enhanced Mode Normal Mode Enhanced Mode Note 1 IOL / IOH 4 mA -0.4 mA 4.0 mA -0.5 mA 6 mA -2 mA 1.5 mA -0.5 mA 3.0 mA Note 1 Note 1 Note 1 Note 1 Notes
NOTES: 1. The CPUPWRGD, SERR#, PIRQ[A:H], GPIO22/CPUPERF, APIC[1:0], SMBDATA, SMBCLK and SMLINK[1:0] signals have an open drain driver, and the VOH specification does not apply. These signals must have external pull-up resistors.
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Table 41. Other DC Characteristics
Symbol V5REF VCC3_3 VCC1_8 HUBREF Vcc(RTC) VIT+ VITVDI VCM VCRS VSE ILI1 ILI2 ILI3 Parameter ICH2 Core Well Reference Voltage I/O Buffer Voltage Internal Logic Voltage Hub Interface Reference Voltage Battery Voltage Hysteresis Input Rising Threshold Hysteresis Input Falling Threshold Differential Input Sensitivity Differential Common Mode Range Output Signal Crossover Voltage Single Ended Rcvr Threshold Input Leakage Current Hi-Z State Data Line Leakage Input Leakage Current - Clock signals Input Capacitance - Hub interface Input Capacitance - All Other COUT CI/O CL Output Capacitance I/O Capacitance Crystal Load Capacitance 0.2 0.8 1.3 0.8 -1.0 -10 -100 2.5 2.0 2.0 +1.0 +10 +100 Min. 4.75 3.102 1.7 0.48 x (Vcc1.8) 0.64 x (Vcc1.8) 2.0 1.9 1.3 Max 5.25 3.498 1.9 0.52 x (Vcc1.8) 0.70 x (Vcc1.8) 3.6 Unit V V V V V V V V V V V V A A A (0 V< VIN< 3.3V) See Note Applied to USBP[1:0][P:N] Applied to USBP[1:0]P:N] |(USBPx+,USBPx-)| Includes VDI Normal Mode Enhanced Mode Notes
CIN
8 12 12 12
pF pF pF pF
FC = 1 MHz FC = 1 MHz FC = 1 MHz 2.5 - 6 pF Typical
NOTES: 1. Includes APICCLK, CLK14, CLK48, CLK66, LAN_CLK and PCICLK
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4.4
AC Characteristics
Table 42. Clock Timings (Sheet 1 of 2)
Sym Parameter PCI Clock (PCICLK) t1 t2 t3 t4 t5 Period High Time Low Time Rise Time Fall Time Oscillator Clock (OSC) t6 t7 t8 Period High Time Low time USB Clock (USBCLK) fclk48 t9 t10 t11 t12 t13 Operating Frequency Frequency Tolerance High Time Low time Rise Time Fall Time Suspend Clock (SUSCLK) fsusclk t14 t15 Operating Frequency High time Low Time SMBus Clock (SMBCLK) fsmb t18 t19 t20 t21 Operating Frequency High time Low time Rise time Fall time I/O APIC Clock (APICCLK) fioap Operating Frequency 14.32 33.33 MHz 10 4.0 4.7 1000 300 16 50 KHz s s ns ns 2 24 24 24 24 10 10 32 KHz s s 4 4 4 9 9 7 7 1.2 1.2 48 500 MHz ppm ns ns ns ns 1 9 9 9 9 67 20 20 ns 70 ns 9 9 9 30 12 12 3 3 33.3 ns ns ns ns ns 9 9 9 9 9 Min Max Unit Notes Figure
NOTES: 1. The USBCLK is a 48 MHz that expects a 40/60% duty cycle. The source of this PPM is external to this component. 2. The maximum high time (t18 Max) provide a simple guaranteed method for devices to detect bus idle conditions. 3. This specification includes pin-to-pin skew from the clock generator as well as board skew. 4. SUSCLK duty cycle can range from 30% minimum to 70% maximum.
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Table 42. Clock Timings (Sheet 2 of 2)
Sym t22 t23 t24 t25 High time Low time Rise time Fall time Hub Interface Clock fhl t31 t32 t33 t34 t35 Operating Frequency High time Low time Rise time Fall time CLK66 leads PCICLK 6.0 6.0 0.25 0.25 1.0 1.2 1.2 4.5 66 ns ns ns ns 3 9 9 9 9 Parameter Min 12 12 1.0 1.0 Max 36 36 5.0 5.0 Unit ns ns ns ns Notes Figure 9 9 9 9
NOTES: 1. The USBCLK is a 48 MHz that expects a 40/60% duty cycle. The source of this PPM is external to this component. 2. The maximum high time (t18 Max) provide a simple guaranteed method for devices to detect bus idle conditions. 3. This specification includes pin-to-pin skew from the clock generator as well as board skew. 4. SUSCLK duty cycle can range from 30% minimum to 70% maximum.
Table 43. Clock Timings - UART_CLK
Sym t1a t9a t10a t11a t12a t155a Parameter Operating Frequency Frequency Tolerance High Time Low time Rise Time Fall Time 7 7 3 3 Min 14.7456 Max 48 2500 Units MHz PPM ns ns ns ns 9 9 9 9 Notes Fig
Table 44. PCI Interface Timing (Sheet 1 of 2)
Sym t40 t41 t42 t43 Parameter AD[31:0] Valid Delay AD[31:0] Setup Time to PCICLK Rising AD[31:0] Hold Time from PCICLK Rising C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#, PAR, PERR#, PLOCK#, DEVSEL# Valid Delay from PCICLK Rising C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#, PAR, PERR#, PLOCK#, IDSEL, DEVSEL# Output Enable Delay from PCICLK Rising Min 2 7 0 2 11 Max 11 Units ns ns ns ns Min: 0pF Max: 50pF Notes Min: 0pF Max: 50pF Figure 10 11 11 10
t44
2
ns
14
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Table 44. PCI Interface Timing (Sheet 2 of 2)
Sym t45 Parameter C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#, PERR#, PLOCK#, DEVSEL#, GNT[A:B]# Float Delay from PCICLK Rising C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#, SERR#, PERR#, DEVSEL#, Setup Time to PCICLK Rising C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#, SERR#, PERR#, DEVSEL#, REQ[A:B]# Hold Time from PCLKIN Rising PCIRST# Low Pulse Width GNT[A:B}#, GNT[5, 3:0]# Valid Delay from PCICLK Rising REQ[A:B]#, REQ[5, 3:0]# Setup Timer to PCICLK Rising Min 2 Max 28 Units ns Notes Figure 12
t46
7
ns
11
t47 t48 t49 t50
0 1 2 12 12
ns ms ns ns
11 13
Table 45. IDE PIO & Multiword DMA Mode Timing (Sheet 1 of 2)
Sym t60 t61 t62 t63 t64 t65 t66 t67 t68 t69 t70 t71 t72 t73 Parameter PDIOR#/PDIOW#/SDIOR#/SDIOW# Active From CLK66 Rising PDIOR#/PDIOW#/SDIOR#/SDIOW# Inactive From CLK66 Rising PDA[2:0]/SDA[2:0] Valid Delay From CLK66 Rising PDCS1#/SDCS1#, PDCS3#/SDCS3# Active From CLK66 Rising PDCS1#/SDCS1#, PDCS3#/SDCS3# Inactive From CLK66 Rising PDDACK#/SDDACK# Active From CLK66 Rising PDDACK#/SDDACK# Inactive From CLK66 Rising PDDREQ/SDDREQ Setup Time to CLK66 Rising PDDREQ/SDDREQ Hold From CLK66 Rising PDD[15:0]/SDD[15:0] Valid Delay From CLK66 Rising PDD[15:0]/SDD[15:0] Setup Time to CLK66 Rising PDD[15:0]/SDD[15:0] Hold From CLK66 Rising PIORDY/SIORDY Setup Time to CLK66 Rising PIORDY/SIORDY Hold From CLK66 Rising Min 2 2 2 2 2 2 2 7 7 2 10 7 7 7 30 Max 20 20 30 30 30 20 20 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 16 16 15, 16 15, 16 15, 16 15 15 Notes Figure 15, 16 15, 16 15 15 15 16
NOTES: 1. IORDY is internally synchronized. This timing is to guarantee recognition on the next clock. 2. PIORDY sample point from DIOx# assertion and PDIOx# active pulse width is programmable from 2-5 PCI clocks when the drive mode is Mode 2 or greater. Refer to the ISP field in the IDE Timing Register 3. PIORDY sample point from DIOx# assertion, PDIOx# active pulse width and PDIOx# inactive pulse width cycle time is the compatible timing when the drive mode is Mode 0/1. Refer to the TIM0/1 field in the IDE timing register. 4. PDIOx# inactive pulse width is programmable from 1-4 PCI clocks when the drive mode is Mode 2 or greater. Refer to the RCT field in the IDE Timing Register.
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Table 45. IDE PIO & Multiword DMA Mode Timing (Sheet 2 of 2)
Sym t74 t75 t76 Parameter PIORDY/SIORDY Inactive Pulse Width PDIOR#/PDIOW#/SDIOR#/SDIOW# Pulse Width Low PDIOR#/PDIOW#/SDIOR#/SDIOW# Pulse Width High Min 48 Max Units ns 2,3 3,4 Notes Figure 15 15, 16 15, 16
NOTES: 1. IORDY is internally synchronized. This timing is to guarantee recognition on the next clock. 2. PIORDY sample point from DIOx# assertion and PDIOx# active pulse width is programmable from 2-5 PCI clocks when the drive mode is Mode 2 or greater. Refer to the ISP field in the IDE Timing Register 3. PIORDY sample point from DIOx# assertion, PDIOx# active pulse width and PDIOx# inactive pulse width cycle time is the compatible timing when the drive mode is Mode 0/1. Refer to the TIM0/1 field in the IDE timing register. 4. PDIOx# inactive pulse width is programmable from 1-4 PCI clocks when the drive mode is Mode 2 or greater. Refer to the RCT field in the IDE Timing Register.
Table 46. Ultra ATA Timing (Mode 0, Mode 1, Mode 2)
Sym t80 t81 t82 t83 t84 t85 t86 t87 t88 t89 t90 t91 Parameter (1) Sustained Cycle Time (T2cyctyp) Cycle Time (Tcyc) Two Cycle Time (T2cyc) Data Setup Time (Tds) Data Hold Time (Tdh) Data Valid Setup Time (Tdvs) Data Valid Hold Time (Tdvh) Limited Interlock Time (Tli) Interlock Time w/ Minimum (Tmli) Envelope Time (Tenv) Ready to Pause Time (Trp) DMACK setup/hold Time (Tack) 112 230 15 5 70 6 0 20 20 160 20 70 150 Mode 0 (ns) Min Max 240 73 154 10 5 48 6 0 20 20 125 20 70 150 Mode 1 (ns) Min 160 54 115 7 5 30 6 0 20 20 100 20 70 150 Max Mode 2 (ns) Figure Min 120 18 18 18 18 18 18 20 20 17 19 17, 20 Max
NOTE: 1. The specification symbols in parentheses correspond to the Ultra ATA specification name.
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Table 47. Ultra ATA Timing (Mode 3, Mode 4, Mode 5)
Sym t80 t81 t82 t83 t84 t85 t86 t87 t88 t89 t90 t91 Parameter (1) Sustained Cycle Time (T2cyctyp) Cycle Time (Tcyc) (2) Two Cycle Time (T2cyc) Data Setup Time (Tds) Data Hold Time (Tdh) Data Valid Setup Time (Tdvs) Data Valid Hold Time (Tdvh) Limited Interlock Time (Tli) Interlock Time w/ Minimum (Tmli) Envelope Time (Tenv) Ready to Pause Time (Trp) DMACK setup/hold Time (Tack) 39 86 7 5 20 6 0 20 20 100 20 55 100 Mode 3 (ns) Min 90 25 57 5 5 6 6 0 20 20 100 20 55 20 85 20 100 Max Mode 4 (ns) Min 60 16.8 38 4.0 4.6 6.0 6.0 0 75 20 50 Max Mode 5 (ns) Figure Min 40 18 18 18 18 18 18 20 20 17 19 17, 20 Max
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Table 48. Universal Serial Bus Timing
Sym Parameter Min Max Units Notes Fig
Full Speed Source (Note 7) t122 t123 t102 t103 t104 USBPx+, USBPx- Driver Rise Time USBPx+, USBPx- Driver Fall Time Source Differential Driver Jitter To Next Transition For Paired Transitions Source SE0 interval of EOP Source Jitter for Differential Transition to SE0 Transition Receiver Data Jitter Tolerance t105 t106 t107 To Next Transition For Paired Transitions EOP Width: Must accept as EOP Width of SE0 interval during differential transition -18.5 -9 82 14 18.5 9 ns ns ns ns 3 4 22 23 -3.5 -4 160 -2 3.5 4 175 5 ns ns ns ns 2, 3 4 5 22 23 4 4 20 20 ns ns 1, CL = 50 pF 1, CL = 50 pF 21 21
Low Speed Source (Note 8) t122 USBPx+, USBPx- Driver Rise Time 75 300 t123 USBPx+, USBPx- Driver Fall Time Source Differential Driver Jitter t110 t111 t112 To Next Transition For Paired Transitions Source SE0 interval of EOP Source Jitter for Differential Transition to SE0 Transition Receiver Data Jitter Tolerance To Next Transition For Paired Transitions EOP Width: Must accept as EOP Width of SE0 Interval during Differential Transition -25 -14 1.25 -40 25 14 1.50 100 ns ns s ns 2, 3 4 5 22 23 75 300 ns ns ns ns 1, 6 CL = 50 pF CL = 350 pF 1,6 CL = 50 pF CL = 350 pF 21
21
t113 t114 t115
-152 -200 670
152 200
ns ns ns
3 4 5
22 23
210
ns
NOTES: 1. Driver output resistance under steady state drive is specified at 28 ohms at minimum and 43 ohms at maximum 2. Timing difference between the differential data signals 3. Measured at crossover point of differential data signals 4. Measured at 50% swing point of data signals 5. Measured from last crossover point to 50% swing point of data line at leading edge of EOP 6. Measured from 10% to 90% of the data signal 7. Full Speed Data Rate has minimum of 11.97 Mbps and maximum of 12.03 Mbps 8. Low Speed Data Rate has a minimum of 1.48 Mbps and a maximum of 1.52 Mbps
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Table 49. IOAPIC Bus Timing
Sym t120 t121 t122 Parameter APICCD[1:0]# Valid Delay from APICCLK Rising APICCD[1:0]# Setup Time to APICCLK Rising APICCD[1:0]# Hold Time from APICCLK Rising Min 3.0 8.5 3.0 Max 12.0 Units ns ns ns Notes Fig 10 11 11
Table 50. SMBus Timing
Sym t130 t131 t132 t133 t134 t135 t136 t137 t138 Parameter Bus Tree Time Between Stop and Start Condition Hold Time after (repeated) Start Condition. After this period, the first clock is generated. Repeated Start Condition Setup Time Stop Condition Setup Time Data Hold Time Data Setup Time Device Time Out Cumulative Clock Low Extend Time (slave device) Cumulative Clock Low Extend Time (master device) Min 4.7 4.0 4.7 4.0 300 250 25 35 25 10 Max Units s s s s ns ns ms ms ms 1 2 3 25 25 Notes Fig 24 24 24 24 24 24
NOTES: 1. A device will time out when any clock low exceeds this value. 2. t137 is the cumulative time a slave device is allowed to extend the clock cycles in one message from the initial start to stop. If a slave device exceeds this time, it is expected to release both its clock and data lines and reset itself. 3. t138 is the cumulative time a master device is allowed to extend its clock cycles within each byte of a message as defined from start-to-ack, ack-to-ack or ack-to-stop.
Table 51. SIU LPC and Serial IRQ Timings
Sym t150a t151a t152a t153a t154a t155a t157a t157b Parameter SIU_LAD[3:0]/SIU_SERIRQ Valid Delay from SIU_LCLK Rising SIU_LAD[3:0]/SIU_SERIRQ Output Enable Delay from SIU_LCLK Rising SIU_LAD[3:0]/SIU_SERIRQ Float Delay from SIU_LCLK Rising SIU_LAD[3:0]/SIU_SERIRQ Setup Time to SIU_LCLK Rising SIU_LAD[3:0]/SIU_SERIRQ Hold Time from SIU_LCLK Rising SIU_LDRQ# Valid Delay from SIU_LCLK Rising SIU_LFRAME# Setup Time to SIU_LCLK Rising SIU_LAD[3:0] Hold Time from SIU_LCLK Rising 7 0 2 7 0 11 Min 2 2 28 Max 11 Units ns ns ns ns ns ns ns ns Notes Fig 10 14 12 11 11 10 11 11
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Table 52. UART Timings
Sym t150a t150a Parameter SIU0_TXD, SIU1_TXD Valid Delay from UART_CLK Rising SIU0_DTR#, SIU0_RTS#, SIU1_DTR#, and SIU1_RTS# Valid Delay from SIU_LCLK Rising SIU0_RXD, SIU0_CTS#, SIU0_DSR#, SIU0_DCD#, SIU0_RI# SIU1_RXD, SIU1_CTS#, SIU1_DSR#, SIU1_DCD#, and SIU1_RI# Setup Time to SIU_LCLK Rising SIU0_RXD, SIU0_CTS#, SIU0_DSR#, SIU0_DCD#, SIU0_RI#, SIU1_RXD, SIU1_CTS#, SIU1_DSR#, SIU1_DCD#, and SIU1_RI# Hold Time from SIU_LCLK Rising SIU0_CTS#, SIU0_DSR#, SIU0_DCD#, SIU0_RI#, SIU1_CTS#, SIU1_DSR#, SIU1_DCD#, and SIU1_RI# high time SIU0_CTS#, SIU0_DSR#, SIU0_DCD#, SIU0_RI#, SIU1_CTS#, SIU1_DSR#, SIU1_DCD#, and SIU1_RI# low time Min 2 2 Max 13 11 Units ns ns Notes Fig 10 10
t153a
7
ns
11
t154a
0
ns
11
t10a
100
9
t11a
100
9
Table 53. LPC Timing
Sym t150 t151 t152 t153 t154 t155 t156 t157 Parameter LAD[3:0] Valid Delay from PCICLK Rising LAD[3:0] Output Enable Delay from PCICLK Rising LAD[3:0] Float Delay from PCICLK Rising LAD[3:0] Setup Time to PCICLK Rising LAD[3:0] Hold Time from PCICLK Rising LDRQ[1:0]# Setup Time to PCICLK Rising LDRQ[1:0]# Hold Time from PCICLK Rising LFRAME# Valid Delay from PCICLK Rising 7 0 12 0 2 12 Min 2 2 28 Max 11 Units ns ns ns ns ns ns ns ns Notes Fig 10 14 12 11 11 11 11 10
Table 54. Miscellaneous Timings
Sym t160 t161 t162 t163 t164 t165 Parameter SERIRQ Setup Time to PCICLK Rising SERIRQ Hold Time from PCICLK Rising RI#, EXTSMI#, GPI, USB Resume Pulse Width SPKR Valid Delay from OSC Rising SERR# Active to NMI Active IGNNE# Inactive from FERR# Inactive Min 7 0 2 200 200 230 Max Units ns ns RTCCLK ns ns ns Notes Fig 11 11 13 10
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Table 55. Power Sequencing and Reset Signal Timings
Sym t170 t171 t172 t173 t174 t175 Parameter VccRTC active to RTCRST# inactive VccRTC supply active to Vcc supplies active V5Ref active to Vcc3_3, Vcc1_8 active Vcc supplies active to PWROK, VRMPWRGD active AC_RST# active low pulse width AC_RST# inactive to BIT_CLK startup delay Min 5 0 0 10 1 162.8 Max Units ms ms ms ms s ns 3 1, 2 2 Notes Fig 26 26 26, 27 26, 27
NOTES: 1. The V5Ref supply must power up before or simultaneous with its associated 3.3 V supply, and must power down simultaneous with or after the 3.3V supply. See Section 3.3.4 for details. 2. The associated 3.3 V and 1.8 V supplies are assumed to power up or down together. The difference between the levels of the 3.3 V and 1.8 V supplies must never be greater than 2.0V. 3. The Vcc supplies must never be active while the VccRTC supply is inactive.
4.5
Timing Diagrams
Figure 9. Clock Timing
Period High Time 2.0V 0.8V Low Time Fall Time Rise Time
Figure 10. Valid Delay From Rising Clock Edge
Clock
1.5V
Valid Delay
Output
VT
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Figure 11. Setup And Hold Times
Clock
1.5V
Setup Time
Hold Time
Input
VT
VT
Figure 12. Float Delay
Input
VT
Float Delay Output
Figure 13. Pulse Width
Pulse Width
VT
VT
Figure 14. Output Enable Delay
Clock
1.5V
Output Enable Delay
Output
VT
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Figure 15. IDE PIO Mode
CLK66 t61
t60 t75 DIOx#
t76
t69 DD[15:0] Write write data t71 t70 DD[15:0] Read read data
t69
t73 t72 IORDY sample point
t74
t62,t63 DA[2:0], CS1#, CS3#
t64
Figure 16. IDE Multiword DMA
CLK66 t67 DDREQ[1:0] t65 DDACK[1:0] t60 t75 DIOx# t61 t76 t68
t70 DD[15:0] Read
t71 Read Data
Read Data
t69 DD[15:0] Write
t69 Write Data Write Data
id d d
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Figure 17. Ultra ATA Mode (Drive Initiating a Burst Read)
DMARQ (drive) t91
DMACK# (host) t89 STOP (host) t89 DMARDY# (host)
STROBE (drive)
DD[15:0]
DA[2:0], CS[1:0]
Figure 18. Ultra ATA Mode (Sustained Burst)
t82 t81 t85 STROBE @ sender t86 t86 t86 t81 t85
Data @ sender
t83 STROBE @ receiver t84 t84
t83
t84
Data @ receiver
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Figure 19. Ultra ATA Mode (Pausing a DMA Burst)
t90 STOP (host)
DMARDY#
STROBE
DATA
Figure 20. Ultra ATA Mode (Terminating a DMA Burst)
DMARQ (drive)
t88 DMACK# (host)
t91
STOP (host)
DMARDY# (drive) t87 Strobe (host)
DATA (host)
CRC
Figure 21. USB Rise and Fall Times
Rise Time CL Differential Data Lines 10% CL t122 t123 10% 90% Fall Time 90%
Full Speed: 4 to 20 ns at CL = 50 pF
Low Speed: 75 ns at CL = 50 pF, 300 ns at CL = 350 pF
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Figure 22. USB Jitter
Tperiod Crossover Points
Differential Data Lines
Consecutive Transitions Paired Transitions
Figure 23. USB EOP Width
Tperiod Data Crossover Level
Differential Data Lines
EOP Width
Figure 24. SMBus Transaction
t19 t20 t21 SMBCLK t131 t134 t135 t132 t18 t133
SMBDATA
t130
Figure 25. SMBus Time-out
Start t137 CLK ack t138 SMBCLK t138 CLK ack Stop
SMBDATA
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Intel(R) 82801E C-ICH
Figure 26. Power Sequencing and Reset Signal Timings
PWROK, VRMPWRGD T173 Vcc3_3, Vcc1_8, V_CPU_IO V5Ref T171 T172
RTCRST# T170 VccRTC
ich2_powerup_reset_DT.vsd
Figure 27. 1.8 V/3.3 V Power Sequencing
V 3.3
1.8 Voltage
V V < 2.0V
Time
S
t
2
Figure 28. C0 to C2 to C0 Timings
CPU I/F Signals STPCLK# Break Event
T204 T205 T206
ICH2 C0 C2 Ti i d
Unlatched
Latched
Unlatched
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5.0
5.1
Testability
Test Mode Description
The 82801E C-ICH supports two types of test modes, a tri-state test mode and an XOR Chain test mode. Driving RTCRST# low for a specific number of PCI clocks while PWROK is high activates a particular test mode as described in Table 56. Note: RTCRST# can be driven low any time after PCIRST# is inactive.
.
Table 56. Test Mode Selection
Number of PCI Clocks RTCRST# Driven Low After PWROK Active <4 4 5 6 7 8 9 - 24 >24 Test Mode No Test Mode Selected XOR Chain 1 XOR Chain 2 XOR Chain 3 XOR Chain 4 All "Z" Reserved. DO NOT ATTEMPT No Test Mode Selected
Figure 29 illustrates the entry into a test mode. A particular test mode is entered upon the rising edge of the RTCRST# after being asserted for a specific number of PCI clocks while PWROK is active. To change test modes, the same sequence should be followed again. To restore the 82801E C-ICH to normal operation, execute the sequence with RTCRST# being asserted so that no test mode is selected as specified in Table 56. Figure 29. Test Mode Entry (XOR Chain Example)
RSMRST#
PWROK RTCRST# Other Signal Outputs N Number of PCI Clocks Test Mode Entered
All Output Signals Tri-Stated
XOR Chain Output Enabled
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Intel(R) 82801E C-ICH
5.2
Tri-state Mode
When in the tri-state mode, all outputs and bidirectional pin are tri-stated, including the XOR Chain outputs.
5.3
XOR Chain Mode
In the 82801E C-ICH, provisions for Automated Test Equipment (ATE) board level testing are implemented with XOR Chains. The 82801E C-ICH signals are grouped into four independent XOR chains which are enabled individually. When an XOR chain is enabled, all output and bidirectional buffers within that chain are tri-stated, except for the XOR chain output. Every signal in the enabled XOR chain (except for the XOR chain's output) functions as an input. All output and bidirectional buffers for pins not in the selected XOR chain are tri-stated. Figure 30 is a schematic example of XOR chain circuitry. Table 57 - Table 60 list each XOR chain pin ordering, with the first value being the first input and the last value being the XOR chain output. Table 61 lists the signal pins not included in any XOR chain.
Figure 30. Example XOR Chain Circuitry
Vcc
XOR Chain Output Input Pin 1 Input Pin 2 Input Pin 3 Input Pin 4 Input Pin 5 Input Pin 6
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Table 57. XOR Chain #1
(RTCRST# Asserted for four PCI Clocks while PWROK Active) Pin Name SIU0_RXD SIU0_TXD SIU0_CTS# SIU0_DSR# SIU0_DCD# SIU0_RI# SIU0_DTR# SIU0_RTS# SIU1_RXD SIU1_TXD SIU1_CTS# SIU1_DSR# SIU1_DCD# SIU1_RI# SIU1_DTR# SIU1_RTS# SIU_LDRQ# SIU_LAD[3] SIU_LFRAME# SIU_LAD[0] SIU_LAD[1] SIU_LAD[2] SIU_SERIRQ SIU_RESET# LFRAME# /FWH4 FWH3 /LAD3 TP0 FWH0 /LAD0 FWH1 /LAD1 FWH2 /LAD2 THRM# Ball # E17 D19 D17 D18 B20 A21 B19 E16 B18 C17 D16 A18 C16 D15 B16 A16 C15 E14 B15 D14 A15 C14 A14 D13 C13 B13 A12 B12 D12 E12 A11 Notes Top of XOR Chain 1 Second signal in XOR
Table 57. XOR Chain #1
(RTCRST# Asserted for four PCI Clocks while PWROK Active) Pin Name LDRQ0# LDRQ1# GPIO[21] GNTA# /GPIO16 REQB# /REQ5# /GPIO1 GNTB# /GNT5# /GPIO17 GNT1# GNT0# REQA# /GPIO0 PIRQH# PIRQG# /GPIO4 PIRQF# /GPIO3 PIRQE# /GPIO2 PIRQD# PIRQA# PIRQB# PIRQC# REQ0# REQ1# REQ2# GNT2# GNT3# AD_26 AD_30 AD_24 AD_28 TP[2] Ball # B11 C11 A10 B10 Notes
C10
B9 D10 A8 C9 A7 E11 E10 C8 B7 A5 D8 C7 B5 D7 E9 E8 A3 B4 C5 D6 A2 AC2 XOR Chain #1 Output
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Intel(R) 82801E C-ICH
Table 58. XOR Chain #2; Chain 2-1 and Chain 2-2
(RTCRST# Asserted for Five PCI Clocks while PWROK Active) Pin Name AD_18 AD_22 AD_16 STOP# PAR FRAME# AD_20 AD_15 TRDY# AD_11 AD_13 AD_4 AD_9 C/BE[0]# AD_2 AD_6 AD_3 AD_0 AD_5 AD_10 AD_7 AD_1 AD_12 AD_8 SERR# AD_14 PERR# C/BE[1]# DEVSEL# PLOCK# C/BE[2]# IRDY# AD_17 AD_19 AD_23 AD_21 C/BE[3]# AD_25 Ball # D5 B3 B2 D4 C3 B1 C2 D3 E4 F5 C1 D2 E3 F4 G5 F3 G4 E1 H5 F2 F1 H4 G2 H3 G1 H2 J4 H1 J3 K5 J2 K4 K3 K2 K1 L5 L4 L2 Notes Top of XOR Chain 2 Second signal in XOR
Table 58. XOR Chain #2; Chain 2-1 and Chain 2-2
(RTCRST# Asserted for Five PCI Clocks while PWROK Active) Pin Name AD_27 AD_29 AD_31 REQ3# GPIO[6] GPIO[7] GPIO[27] GPIO[28] GPIO[8] GPIO[12] GPIO[13] PCIRST# RESERVED1 GPIO[25] SMBCLK SMBDATA SMBALERT# /GPIO11 NC[11] NC[12] NC[10] SUSCLK USBP0P USBP0N USBP1P USBP1N NC[9] NC[6] NC[7] NC[8] OC1# VSS RESERVED2 TP[1] Ball # L1 M1 M2 M4 M3 N2 N3 N4 P1 P2 P3 R1 P4 R2 T2 R4 U1 U2 T4 V1 U3 U4 T5 W1 V2 W2 V4 W3 Y2 W4 AB2 Y4 AA5 XOR Chain #2 Output, (Chain 2-2) Out XOR Chain 2-1 In XOR Chain 2-2 Notes
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Table 59. XOR Chain #3; Chain 3-1 and Chain 3-2
(RTCRST# Asserted for Six PCI Clocks While PWROK Active) Pin Name SMLINK1 SMLINK0 NC GPIO[24] NC NC FERR# APICD_0 APCID_1 SERIRQ SPKR PDD_6 PDD_7 PDD_8 PDD_9 PDD_5 PDD_10 PDD_4 PDD_11 PDD_13 PDD_3 PDD_12 PDD_1 PDD_2 PDD_14 PDD_0 PDDREQ Ball # AA4 Y5 W7 AB4 Y9 AC7 AA9 AB9 Y10 AA10 AB10 Y11 AA11 AB11 AC11 W12 Y12 AB12 AC12 AB13 AA13 Y13 W13 AC14 AB14 AA14 AC15 Out XOR Chain 3-1 In XOR Chain 3-2 Notes Top of XOR Chain 3 Second signal in XOR
Table 59. XOR Chain #3; Chain 3-1 and Chain 3-2
(RTCRST# Asserted for Six PCI Clocks While PWROK Active) Pin Name PDIOW# PDD_15 PDDACK# PDA_2 IRQ14 SDD_6 PIORDY PDCS1# PDIOR# PDA_0 SDD_8 SDD_9 PDA_1 SDD_7 SDD_5 SDD_10 SDD_4 PDCS3# SDD_11 SDD_2 SDD_12 SDD_3 SDD_13 SDD_1 SDD_14 SDD_0 RI# Ball # Y14 AB15 AA15 AC16 AB16 Y15 AC17 W14 AB17 Y16 AA17 AB18 W15 AC18 W16 Y17 AA18 AC19 AB19 AC20 Y18 AA19 AB20 AC21 W17 Y19 R5 XOR Chain #3 Output, (Chain 3-2) Notes
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Intel(R) 82801E C-ICH
Table 60. XOR Chain #4; Chain 4-1 and Chain 4-2
(RTCRST# Asserted for Seven PCI Clocks While PWROK Active) Pin Name SDIOR# SDDREQ SDIOW# SDD_15 SDA_1 SDDACK# IRQ15 SIORDY SDA_2 SDCS3# SDA_0 SDCS1# VRMPWRGD GPIO[18] GPIO[19] GPIO[20] GPIO[22] GPIO[23] A20GATE RCIN# CPUPWRGD INIT# SMI# CPUSLP# IGNNE# NMI INTR A20M# STPCLK# HL7 HL5 HL6 HL4 H1REQM Ball # W18 AC22 W19 Y20 AA21 V19 AB22 V20 W20 Y21 AB23 U19 W21 Y22 AA23 T19 U20 T20 Y23 W23 V22 U21 T21 R19 V23 U22 U23 T23 T22 P19 P20 R23 N19 P22 Notes
Table 60. XOR Chain #4; Chain 4-1 and Chain 4-2
(RTCRST# Asserted for Seven PCI Clocks While PWROK Active) Pin Name H1STOP HL_STR# HL_STR H1REQI HL3 HL2 HL1 HL0 H1PAR HLCOMP LAN1_RXD[1] LAN1_TXD[0] LAN1_TXD[1] LAN1_TXD[2] LAN1_RXD[0] EE1_DOUT LAN1_RXD[2] LAN1_RSTSYNC EE1_SHCLK EE1_DIN EE1_CS LAN0_RXD[1] LAN0_RXD[2] LAN0_RSTSYNC EE0_DOUT EE0_SHCLK EE0_CS EE0_DIN LAN0_RXD[0] LAN0_TXD[2] LAN0_TXD[1] LAN0_TXD[0] OC0# Ball # N21 N23 M22 M19 M20 L23 L21 L19 K22 K19 G23 H21 G21 E23 H20 G20 E22 D23 C23 E21 F20 H19 B23 C22 D21 E20 F19 G19 C21 D20 A22 C20 AA1 XOR Chain #4 Output, (Chain 42) Out XOR Chain 4-1 In XOR Chain 4-2 See Section 5.3.1.1 Notes See Section 5.3.1.1
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Table 61. Signals Not in XOR Chain
Pin Name APICCLK CLK14 CLK48 CLK66(HCLK) PCICLK SIU_LCLK UART_CLK LAN1_CLK LAN0_CLK INTRUDER# Ball # AC9 W11 AB8 J23 M5 E13 A19 B21 F22 AB5 Notes
Table 61. Signals Not in XOR Chain
Pin Name PWROK RSMRST# RTCX1 RTCX2 RTCRST# TP[2] RSM_PWROK TP[1] OC0# RI# Ball # W9 Y8 Y7 AA7 AA6 AC2 T3 AA5 AA1 R5 Notes
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Intel(R) 82801E C-ICH
5.3.1
XOR Chain Testability Algorithm Example
XOR chain testing allows motherboard manufacturers to check component connectivity (e.g., opens and shorts to VCC or GND). An example algorithm to do this is shown in Table 62.
Table 62. XOR Test Pattern Example
Vector 1 2 3 4 5 6 7 Input Pin 1 0 1 1 1 1 1 1 Input Pin 2 0 0 1 1 1 1 1 Input Pin 3 0 0 0 1 1 1 1 Input Pin 4 0 0 0 0 1 1 1 Input Pin 5 0 0 0 0 0 1 1 Input Pin 6 0 0 0 0 0 0 1 XOR Output 1 0 1 0 1 0 1
In this example, Vector 1 applies all "0s" to the chain inputs. The outputs being non-inverting, will consistently produce a "1" at the XOR output on a good board. One short to Vcc (or open floating to Vcc) will result in a "0" at the chain output, signaling a defect. Likewise, applying Vector 7 (all "1s") to the chain inputs (given that there are an even number of input signals in the chain), will consistently produce a "1" at the XOR chain output on a good board. One short to Vss (or open floating to Vss) will result in a "0" at the chain output, signaling a defect. It is important to note that the number of inputs pulled to "1" will affect the expected chain output value. If the number of chain inputs pulled to "1" is even, then expect "1" at the output. If the number of chain inputs pulled to "1" is odd, expect "0" at the output. Continuing with the example in Table 62, as the input pins are driven to "1" across the chain in sequence, the XOR Output will toggle between "0" and "1." Any break in the toggling sequence (e.g., "1011") will identify the location of the short or open.
5.3.1.1
Test Pattern Consideration for XOR Chain 4
When the 82801E C-ICH is operated with the Hub Interface in "Normal" mode (See "Functional Straps" on page 49), the HL_STB and HL_STB# signals must always be driven to complementary logic levels. For example, if a "1" is driven on HL_STB, then a "0" must be driven on HL_STB# and vice versa. This will need to be considered in applying test patterns to this chain. When the 82801E C-ICH is operated with the Hub Interface in "Enhanced" mode there are no restrictions on the values that may be driven onto the HL_STB and HL_STB# signals.
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